DEC Marlboro JUNE 1981 KSREF.MEM for hardware REV 4 *************************************************************************** *** Hardware REV 4 changes included in stars *** *************************************************************************** COPYRIGHT (C) 1978 DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS. THIS SOFTWARE IS FURNISHED UNDER A LICENSE FOR USE ONLY ON A SINGLE COMPUTER SYSTEM AND MAY BE COPIED ONLY WITH THE INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE, OR ANY OTHER COPIES THEREOF, MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY OTHER PERSON EXCEPT FOR USE ON SUCH SYSTEM AND TO ONE WHO AGREES TO THESE LICENSE TERMS. TITLE TO AND OWNERSHIP OF THE SOFTWARE SHALL AT ALL TIMES REMAIN IN DEC. THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT CORPORATION. DEC ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS SOFTWARE IN EQUIPMENT WHICH IS NOT SUPPLIED BY DEC. CONTENTS Page 2 ________ Chapter Subject Page -------- -------------------------------------- ------- 8080 CONSOLE ( 8080 ) Overview 1-2 CONSOLE ( 8080 ) Commands 1-3 EB Command Truth Table 1-5 CONSOLE Error Codes 1-7 ERROR-mesages-during-BOOTING 1-10 8080 <-> MONITOR Communication Area 1-11 CONSOLE Register contents 1-12 EC ( 8080 ) m-code breakdown 1-18 Processor KS10 Processor Status Words 2-2 UPT / EPT layout for TOP10 / TOPS20 2-5 KS10 I/O Instruction format 2-6 Internal register bit format 2-7 External register bit format 2-14 ECC ( MOS memory error correction ) bits 2-18 UNIBUS Signal pin finder 2-19 Peripherals Device adresses and Vectors for KS10 3-2 KS10 option jumper and switch settings 3-3 UART baud rate settings for CONSOLE 3-4 Device command function codes 3-5 RH11 RP04/5/6 register format 3-6 RH11 RM03 register bit format 3-7 RM03 / RP06 / RH11 register in english 3-8 RH11 TM02/TM03 register bit format 3-9 Magtape registers in english 3-10 DZ-Control registers 3-12 LP20/LP05/LP14 Bit Format 3-14 CD11 Bit Format 3-16 DUP11 Bit Format 3-17 Unibus Adapter Mini Check 3-19 Micro machine The micro-code HALT-status block 4-2 m-code field listing format 4-3 Dispatch ROM definitions 4-4 KS10 m-word bits sorted by physical bit 4-5 KS10 m-word bits sorted by function 4-8 Debugging DDT bits and pieces 5-2 UNIBUS adapter wrap around test 5-8 descriptions descriptions of 8080 - sequences 6-2 UBA-RH11 DESCRIPTION OF UBA-RH11 READ-WRITE 7-1 CHAPTER 1 8080 CONSOLE Page 1-2 _______ The console (CSL) board, contains the main clock source, and arbitrates access to the backpanel bus, as well as the 8080 based console hardware. The operator controls the machine via console functions typed in via the console terminal to the 8080; he may load and check microcode; read and write memory; stop and start the clock; single step the clock; halt the machine; start at a given location; execute an instruction, etc. It does not have quite the power of the KL10 console, in that he does not have all the diagnostic features; he cannot, for example, read the PI status at any instant, nor can he at any given instant, read the VMA or PC registers or read the AC's. (Many registers, in fact, are internal to the 2901, and are not available even were the board on an extender module and an oscilloscope available.) [However, when entering the halt loop, either upon executing a halt instruction or when requested to stop by the 8080, the microcode deposits the Halt Status Block , to make these available to the console, as well as the reason for halting, before interrupting the 8080. Thus the operator does have this information available via the microcode, if not by diagnostic hardware. The console has the same access to the backpanel as the CPU, and can therefore read or write any memory locations, and initiate any I/O that the CPU can (except I/O to the internal CPU registers PI and APR). These it may also do, if the microcode is loaded and the CPU is functional, by executing the required I/O instruction. The console may also load microcode (2K x 96 bits), read it back to check it, and has access to the same diagnostic points as are available to the KL10 console. Thus the operator can read the current microcode location, next location, current top of stack, etc. At power-up, the console may load microcode automatically from the disk, or may be programmed to wait for console commands to do so . On initial power-up , the PROM-program will wait 30 seconds before initiating an AUTO-BOOT ( message "BT AUTO ). A CONTROL-C or any character will abort the 30 second-wait and give the KS-prompt "KS10 " . The AUTO-BOOT can also be inhibited by pushing the " BOOT button " , this will echoe as " BT SW " and will cause an immediate BOOT . *************************************************************************************************************************************** In PROM version 4, the powerfail recovery code (battery back-up) was taken out. The KS10 will always do a reload after a *** *** POWERFAIL. The KS10 will appear as though it is going through the normal boot sequence when the power is restored. You will *** *** have to ENTER TIME AND DATE if you choose to allow the OPERATING SYSTEM to boot. If you wish to abort the AUTO-BOOT sequence *** *** after a power fail, just do a CONTROL-C at the CTY. *** ************************************************************************************************************************************ ************************************************************************************************************************************ *** Several 8080 bugs were fixed with this version of the PROM code (VER 5.2). With REV 3 (PROM VER 4.2), there were various *** *** KLINIK related bugs. The KS10 also had a problem obtaing a correct HALT STATUS BLOCK after a BUGHLT. There were problems *** *** with HUNG KS10'S after a powerfail in which the 8080 code was partially responsible. SMBOOT also had alot to do with the *** *** problem and is now patched to correct this condition (RED PACK VER 405 has the patch). The ?NXM message which appeared on *** *** the CTY after an AUTO-BOOT has been fixed. PROM version 5.2 fixes all these problems. *** ************************************************************************************************************************************ CSL-COMMANDS CURRENTLY IMPLEMENTED CSL V5 Page 1-3 ____________ _________ ___________ ___ __ NOTE: Several commands may be put on a single line , separated by commas ^\ ;enter CONSOLE mode ^U ;rub out current line ^O ;switch: first one stops cty-output , second one resumes cty-output ^S ;stop tty-output and hangs 8080 waiting for CONTROL-Q ( see below ) ^Q ;resumes tty-output ^C ;stops whatever the 8080 is doing ^Z ;Enter USER-mode RUB-OUT ;rub out previous character typed BC ;short for BOOTCHECK - floats 1's and 0's across KS10 BUS , checks page 1 of KS10 MOS-memory in an ;addressing sequence , and also for ability to hold all 1's and 0's . Checks KS10 control-store via an ;addressing sequence for testing CRAM addressing and also all locations for ability to hold all 1's and ;all 0's. ;Beware: The BC-command will usually leave the entire KS10 control-store containing BAD PARITY . If the ;BC-command is allowed to run to completion , or should FAIL during the CRAM portion of its testing ;subsequent EXAMINES of control-store will yield PARITY ERRORS ! This is not necessarily because the ;KS10 has a problem , but because the control-store has intentionally been loaded with bad parity. ; ;The BC-command should be followed with a B2-command , which will attempt to load the control-store with ;the KS10 micro-code . This should eliminate the parity errors . If it does not ,You can always try ;clearing the control-store by typing a sequence of commands at the "KS10>" prompt : ; Typein: MR,LC 0,DC 0 ; DN 0,RP .... and then wait for 60 seconds ; "Control C" to break the indefinite repeat ; .... The "typical" execution time of BC-command is long ---- roughly 3 minutes ---- BT ;Boot SYSTEM -- load CRAM from designated disk ( see DS ) via memory then ;load monitor boot from disk ( block/track/sector 0 ) and start at 1000 BT 1 ;same as BT , but loads SMMON and starts at 20000 B2 ; short for BOOTCHECK 2 . Loads a modified PRE-BOOT program , which loads a special sequence of modified ;functional diagnostics. CE X ;CACHE enable 0=OFF 1=ON current state? CH ;CPU clock halt CO ;continue(causes m-code to leave HALT-loop ) CP XX ;CPU clock pulse (xx NR of pulses -- default 1 pulse ) CS ;CPU clock start DB XX ;deposit BUS , XX data DC XX ;deposit CRAM , XX is at least 32 octal characters DF XX ;write m-code bits according to last LF-command DK XX ;deposit 8080 loc ( only RAM locs stick ) DI XX ;deposit I/O , XX data DM XX ;deposit MEMORY , XX data DN XX ;deposit next ( depending on last DK , DM or DI ) XX data DR ;deposit internal 8080 I/O register DS ;Disk select. Command to specify UNIT NUMBER ,RHBASE ( 1 or 3 ) and UNIBUS ADAPTER to ;load from when booting EB ;examine BUS and 8080 control registers (READS IO REGISTERS 100,303,103) CSL-COMMANDS CURRENTLY IMPLEMENTED CSL V5 Page 1-4 ____________ _________ ___________ ___ __ EC XX ;examine CRAM at address XX EC ;examine CRAM ..curr. Control reg , no clocks .. current loc as addr. EK ;examine 8080 location EK XX ;examine 8080 address XX EI ;examine I/O ( last I/O address specified ) EI XX ;exmaine I/O address XX EJ ;examine jumps -- prints CRAM address signals ( CURR , NXT , J , SUB ) EM ;examine MEMORY ( last MEMORY location specified ) EM XX ;examine MEMORY location XX EN ;examine next ( either from last EK , EM or EI ) ER ;examine internal 8080 I/O register EX XX ;execute KS10 instruction XX FI ;indirect FILE command ( not used yet , but may be !!) HA ;HALT KS10 ( execute HALT-instruction -causes m-code to write HSB and then to enter HALT-loop ) KL ;Klinik-Command ,0=disable , 1=enable , nothing=state ( on/off ) LA XX ;set memory address LB ;load bootstrap from designated disk ( see DS ) block/track/sector 0 LB 1 ;load diagnostic monitor SMMON LC XX ;set CRAM address LF XX ;selects a set ( 0-7 ) of 12 bits of m-code (see note at end ****) LI XX ;set I/O address LK XX ;set 8080 address LR ;set internal 8080 I/O register LT ;lamp test ,lights three lamps of front panel MB ;load only boots-trap of currently selected magtape MK XX ;marks micro-code location XX ( sets bit 95) MM ;set KLINIK state into APT-protocol (beware--not in the FIELD !!) MR ;MASTER RESET MS ;Magtape Select. Command to specify UNIT NUMBER , RH BASE , UNIBUS ADAPTER, ;SLAVE NUMBER and DENSITY of magtape YOU would like to boot from ;The "UNIT?" message has been shortened to "TCU?" -- short for " Tape ;Control Unit ?". MT ;Boot System from selected magtape MT 1 ;BOOT diagnostic monitor SMMAG from magtape PE X ;enable parity ( 00=disable 7=enable all 1=DP-par 2=CRM-par ; 4=clock-par error stop PM ;pulse m-code ( issue single CP & EJ ) PW ;clears KLINIK password , or sets it ( 6 char's max ) RC ;read CRAM direct , functions 0-17 ( no resets, no load diag addr , no CPU clock ) ( see note at end ****) RP ;repeat - repeats last command , or line of commands which it delimits ;any character ( except CNTRL-O ) typed will stop repeat ;CNTRL-O acts as switch ( first one= stop output , next one=resume output) ;EXAMPLE: EM 0,EK 0 , EC 0,RP will repeat execution of this line SC ; command enables/disables SOFT CRAM ERROR recovery ( x=0 off , x=1 on SC=state of switch ) CSL-COMMANDS CURRENTLY IMPLEMENTED CSL V5 Page 1-5 ____________ _________ ___________ ___ __ SI ;single instruction SH ;SHUTDOWN ( deposit non-zero data in memory location 30 ) ;causing TOPS20 to shut down without warning SM XX ;start m-code at XX ( SM 1 causes dump of HALT-status block !!) ;Default is 0 -- Start m-code ST XX ;start KS10 at address XX TE X ;1 MSEC enable. 0= OFF , 1=ON , current state? TP X ;TRAPS enable 0=OFF , 1=ON (enables paging ) , current state? TR XX ;TRACE - repeats CP & EJ commands till any character typed ;XX ( if typed ) is desired CRAM stop-adress TT ;tranfer KLINIK-line to USER-MODE UM XX ;unmarks micro-code location XX VD ;verify CRAM ( using same load-path as previous ) from disk VT ;verify CRAM ( using same load-path as previous ) from magtape ZM ;zero KS10 MOS memory ( beware --- slow ) *********************************************************************** ************ EB COMMAND TRUTH TABLE ************* *********************************************************************** * * * 100 * 303 * 103 * TRUE STATE * * * * 0X * XXX * XXX * CSL REC PE * * X0 * XXX * XXX * UBA3 PE * * XX * XX0 * XXX * MEM PE * * XX * X0X * XXX * CR/M PE * * XX * XXX * XX0 * UBA 2 PE * * XX * XXX * X0X * CRA PE * * XX * XXX * 0XX * DP PE * * * XX * XXX * XX0 * DPM PE * * * XX * XXX * X0X * DPE/M CLK ENB * * * XX * XXX * 1XX * CRAM CLK ENB * * * 0X * XXX * XXX * UBA 1 PE * * * X0 * XXX * XXX * UBA 4 PE * *********************************************************************** 0 = LOW 1 = HIGH CSL-COMMANDS CURRENTLY IMPLEMENTED CSL V5 Page 1-6 ____________ _________ ___________ ___ __ ***** LF-command CRAM Bits RC-Command CRAM Data -------------------- --------------------- LF CRAM bits RC Data -- --------- -- ------------------------------ 0 00-11 0 CRAM bits 00-11 1 12-23 1 Next CRAM address 2 24-35 2 CRAM subroutine return address 3 36-47 3 current CRAM address 4 48-59 4 CRAM bits 12-23 5 60-71 5 CRAM bits 24-35 ( Copy A) 6 72-83 6 CRAM bits 24-35 ( Copy B) 7 84-95 7 0s 10 Parity bits A-F 11 KS10 bus bits 24-35 12 CRAM bits 36-47 ( Copy A) 13 CRAM bits 36-47 ( Copy B) 14 CRAM bits 48-59 15 CRAM bits 60-71 16 CRAM bits 72-83 17 CRAM bits 84-95 8080-CONSOLE-ERROR-CODES Page 1-7 ________________________ ?A/B A & B copies of CRAM bits did not match ?BC BOOT check failed ?BFO Input buffer overflow ?BN received bad number on input ?BT device error or timeout during BOOT operation ?BUS BUS polluted on power up ?CHK PROM checksum failed ?DNC did not complete HALT ?DNF did not finish instruction ?IA illegal argument ( address out of range etc ) ?IL ILLEGAL Instruction ?KA KEEP ALIVE failed ?MEM REFRSH ERR memory refresh error ( MEM BUSY stayed set too long , because it didn't release data on a write to memory The message "?MEM REFRSH ERR" has been shortened to "?MRE" short for Memory Refresh Error ? ?NA KLINIK Link Not Available ?NBR Console was not granted BUS on a request ?NDA received no data acknowledge on mem request ?NR-SCE Non-Recoverable CRAM-Error detected by Soft Cram Error recovery - A CRAM Error is not recoverable , if it occurs while memory is busy , or causes a "MRE" , or if the disk is in a condition , which the PROM-program can not save and later restore ?NXM referenced nonexistent memory location ?PAR ERR report clock-freeze due to parity error and type out READ IO of 100,303,103 This message occurs on any non CRA/CRM parity errors , and also occurs if a CRA/CRM parity error happens at the same address twice in a row . ( i.ethe PROM program assumes , that , if the error happened twice in a row at the same location , it must be a hard bit failure and recovery could never be achieved ?PWL Password length error ?RA command requires argument ( YOU gotta type something ) ?RUNNING trying to do a command , that may screw up ?UI unknown interrupt 8080-CONSOLE-ERROR-CODES Page 1-8 ________________________ OTHER 8080 CONSOLE MESSAGES --------------------------- BUS 0-35 message header for EB command BT AUTO beginning Auto Boot sequence ( 15 sec after power-up) BT SW message says BOOTING , using BOOT switch C CYC typed on DB-command if COM/ADR cycle blew CYC cycle type for DB command HLTD message "HALTED/XXXXXX " where xxxxxx is data KS10> prompt message OFF message , says this signal is off ON message , says this signal is on PC Program Counter ( what else ) RCVD data received on bus SCE xxxxxx Soft Cram Error recovery performed and xxxxxx stands for the error-address . SENT data sent to bus >>UBA? query for unibus adapter >>UNIT? query for unit to use >>RHBASE? query for RH11 to use >>DENS? query tape density >>SLV? query tape slave 8080-ERror-messages-during-BOOTING Page 1-9 __________________________________ On an error-condition , detected by the 8080 , the Fault-light will go on and a message of the form ?BT XXXYYY will be printed on the CTY. The following error-codes are only "rough" pointers , they can be caused by any of the following problems: Disk not a disk at all , wrong unit selected ( DS-command ! ) , Home blocks not readable or not there Home blocks not set by SMFILE for 8080 , 8080 File-system garbage ****************************************************************************************************************************** *** Disk: *** *** XXX=001 Disk error encountered while trying to read HOME-blocks *** *** *** *** XXX=002 Disk error encountered while trying to read the page of *** *** pointers , which make up the "8080-File-System" *** *** *** *** xxx=003 Disk error encounterd while trying to read a page of *** *** m-code *** *** *** *** xxx=004 Microcode did not successfully start up -- usually after BT- , MT- , MB- ,or LB-command *** *** also after LB , before system-micro code has been loaded. *** *** *** *** xxx=010 Disk error encountered while trying to read PRE-BOOT *** *** *** *** yyy are the lower 8 bits of the 8080 adress of the failing "Channel Command List" operation. Normally it is here *** *** a good bet to do an "EI" to get the contents of the RH11 register that has the error-bits set ! *** *** *** *** Magtape: *** *** *** *** The following ERROR-messages can point to the following problem-areas: *** *** *** *** Magtape is no magtape at all ,wrong unit selected ( see MS-command ) ,Magtape is not bootable ( no m-code , *** *** no PRE-BOOT ) *** *** *** *** xxx=001 Error trying to read m-code first page *** *** *** *** xxx=003 Error trying to read additional pages of m-code *** *** *** *** xxx=004 .... see disk-error description above ... *** *** *** *** xxx=010 Error trying to read in PRE-BOOT program *** *** *** *** yyy see above ( disk-section ) *** ****************************************************************************************************************************** 8080-ERror-messages-during-BOOTCHECK Page 1-10 ____________________________________ ****************************************************************************************************************************** *** BOOTCHECK ERROR-messages are of the form: ?BC WWYYYY *** *** *** *** WW=00 Indicates a failure during the KS10-Bus-check . BOOTCHECK is floating a ONE and then a ZERO across the *** *** KS10-BUS. YYYY will be the failing BIT , in OCTAL --- Numbers will range from 0 to 43 , corresponding *** *** to DECIMAL 0-35. *** *** *** *** WW=04 Indicates a failure during the MEMORY-check . BOOTCHECK is trying to verify page1 of MOS-memory and tests *** *** address 1000-1777 for ability to hold all ONES and all ZEROES , and to sequence thru that page of memory *** *** correctly . YYYY will be the failing memory address. *** *** *** *** WW=10 Indicates a failure during the CRAM-check portion of BOOTCHECK . YYYY will be the failing CRAM-address *** ****************************************************************************************************************************** Error-messages-out-of-PRE-BOOT Page 1-11 ______________________________ PRE-BOOT is loaded from Disk or Magtape ( see 8080 commands DS , MS , BT , BT 1 , MT , MT 1 ) PRE-BOOT is written onto the disk using "SMFILE.EXE" , it also is written on "standard" Diagnostic-tapes and onto the "MONITOR-DISTRIBUTION"-tapes. PRE-BOOT is loaded by the 8080 into MEMORY-locations 1000 and up , and starts at 1000 . The ERROR-halts are: 1001 found "bad" core-transfer address ( page 1 is illegal - cant overload PRE-BOOT ) 1003 No RH11 Base Address 1004 Magtape Skip failure 1002 all other failures At ERROR-halt time the following MEMORY-Locations contain the useful INFO : Disk-Booting Magtape-Booting ------------ --------------- 100 "8080" disk-address Not used 101 Memory transfer address same 102 Index-pointer same 103 RPCS1-register MTCS1-register 104 RPCS2-register MTCS2-register 105 RPDS - register MTDS - register 106 RPER1-register MTER1-register 107 RPER2-register (RP06 only ) Not used 110 RPER3-register Not used 111 UBA Page RAM loc 0 same 112 UBA-status register same 113 Version Nr. of PRE-BOOT same Note: The Version Nr. of PRE-BOOT will be the same as the Version Nr. of SMFILE. The "8080" disk-adress is in the form " CY SA TA " THEREBY IT WILL BE POSSIBLE TO ASK A CUSTOMER WITH A PRE-BOOT FAILURE , TO DO AN : EM 77 EN,RP ...... AND TYPE SOMETHING AFTER ADRESS 115 .... AND THEN TELL US WHAT HE SEE'S 8080-Communication-Area ( CORE ) Page 1-12 _______________________ _ ____ _ The 8080 maintains and services an in-core communication area. Currently used are words 31 to 40. Word Nr. Meaning ____ ___ _______ 31 Keep Alive and Status word 32 KS-10 CTY input word ( from 8080 ) 33 KS-10 CTY output word ( to 8080 ) 34 KS-10 KLINIK user input word ( from 8080 ) 35 KS-10 KLINIK user output word ( to 8080 ) 36 BOOT RH-11 Base Address 37 BOOT Drive Number 40 Magtape Boot Format and Slave Number Word 31 Keep Alive and Status word ____ __ Bit 4 Reload Bit 5 Examine Keep Alive Bit 6 KLINIK active Bit 7 PARITY Error detect enabled Bit 8 CRAM Parity Error detect enabled Bit 9 DP Parity Error detect enabled Bit 10 CACHE enabled Bit 11 1 msec enabled Bit 12 TRAPS enabled Bit 20-27 Keep Alive Bit 32 BOOT SWITCH BOOT Bit 33 POWER FAIL BIT 34 Forced RELOAD BIT 35 Keep Alive failed to change Word 32 KS-10 CTY input word ( from 8080 ) ____ __ Bits 20-27 0 --- no action , 1 --- CTY character pending Bits 28-35 CTY-character Word 33 KS-10 CTY output word ( to 8080 ) ____ __ Bits 20-27 0 --- no action , 1 --- CTY character pending Bits 28-35 CTY-Character Word 34 KS-10 KLINIK user input word ( from 8080 ) ____ __ Bits 20-27 0 --- no action , 1 --- KLINIK character , 2 --- KLINIK active , 3 --- KLINIK carrier loss Bits 28-35 KLINIK-Character Word 35 KS-10 KLINIK user output word ( to 8080 ) ____ __ Bits 20-27 0 --- no action , 1 --- KLINIK character , 2 --- Hangup request Bits 28-35 KLINIK-Character OUTPUT process KS10 ==> 8080 ---------------------------- Load character and flag into 33 , set 8080-interrupt , 8080 examines 33 and gets character , clears interrupt , sends character to hardware , clears 33 and sets KS-10 interrupt. INPUT process 8080 ==> KS10 --------------------------- 8080 gets interrupted "TTY-char available" , 8080 gets character and delivers into input-word ( 31 ) with flag(s) and sets KS-10 interrupt. Console-Register-contents Page 1-13 _________________________ READ-I/O=0 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! !R DATA 28 ! R DATA 29 ** R DATA 30 ! R DATA 31 ! R DATA 32 ** R DATA 33 ! R DATA 34 ! R DATA 35 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** READ-I/O=1 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! !R DATA 20 ! R DATA 21 ** R DATA 22 ! R DATA 23 ! R DATA 24 ** R DATA 25 ! R DATA 26 ! R DATA 27 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** READ-I/O=2 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! !R DATA 12 ! R DATA 13 ** R DATA 14 ! R DATA 15 ! R DATA 16 ** R DATA 17 ! R DATA 18 ! R DATA 19 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** READ-I/O=3 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! !R DATA 4 ! R DATA 5 ** R DATA 6 ! R DATA 7 ! R DATA 8 ** R DATA 9 ! R DATA 10 ! R DATA 11 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** READ-I/O=100 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! CSL ! ** ! ! ** ! ! ! ! REC PE ! UBA3 PE ** SPARE ! CR/M ! MEM ** DP PARITY ! CRA PARITY ! UBA2 PE ! ! ! ** ! PARITY ERR ! PARITY ERR ** ERR L ! ERR L ! ! ! L ! L ** L ! L ! L ** ! ! L ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** Console-Register-contents Page 1-14 _________________________ READ-I/O=101 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! MMC REF ! ! PI REQ 1 ! PI REQ 2 ** PI REQ 3 ! PI REQ 4 ! PI REQ 5 ** PI REQ 6 ! PI REQ 7 ! ERR B ! ! ! ** ! ! ** ! ! H ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** READ-I/O=102 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! R AC LO ! R RESET ** R MEM BUSY ! R I/O BUSY ! R BAD DATA ** R COM ADR ! R I/O DATA ! R DATA ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** READ-I/O=103 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! UBA1 PE ! UBA4 PE ** R PAR RIGHT ! R PAR LEFT ! R DATA 0 ** R DATA 1 ! R DATA 2 ! R DATA 3 ! ! L ! L ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** READ-I/O=300 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! CTY ! CTY CHAR ** REMOTE DIAG ! REMOTE DIAG ! CSL4 ** RUN (1) ! EXECUTE ! CONTINUE ! ! STOP BIT #! LENGTH ** STOP BIT # ! CHAR ! HALT LOOP ** H ! H ! H ! ! (SW) ! (SW) ** (SW) ! LENGTH ! ** ! ! ! ! ! ** ! (SW) ! ** ! ! ! ****************************************************************************************************************************** READ-I/O=301 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! 10 ! NXM ** SPARE ! BUS ! PE (1) ** CONSOLE ! BOOT ! DATA ACK ! ! INTERRUPT ! H ** ! REQ ! OCCURRED ** ENABLE H ! H ! H ! ! H ! ** H ! ! H ** (SW) ! (SW) ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** Console-Register-contents Page 1-15 _________________________ READ-I/O=302 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! REMOTE ** REMOTE EN ! TERMINAL ! REMOTE DIAG ! ! 0 ! 0 ** 0 ! 0 ! PROTECT H ** H ! CARRIER ! CARRIER ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** READ-I/O=303 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! R CLK ** CRAM ! DPE/M ! ! ! 0 ! 0 ** 0 ! 0 ! ENB (0) H ** CLK ENB ! CLK ENB ! DPM PAR ERR ! ! ! ** ! ! ** H ! L ! ERR L ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT-I/O=204 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** CRAM ! CRM ADR ! SS ** DP ! STACK ! CRAM ! ! 0 ! 0 ** WRITE ! LOAD ! MODE ** RESET ! RESET ! RESET ! ! ! ** ! ! ** H ! H ! H ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT-I/O=205 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! 0 ! 0 ** ! TRAP ! diag 10 ** DIAG 4 ! DIAG 2 ! DIAG 1 ! ! ! ** ! EN ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT-I/O=206 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! 0 ! 0 ** 0 ! 0 ! 0 ** 0 ! SINGLE ! CLK RUN ! ! ! ** ! ! ** ! CLK H ! H ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** Console-Register-contents Page 1-16 _________________________ WRT-I/O=210 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! CHECK ! CONSOLE ** T ENB ! T ENB ! CRA T CLK ** CRA R CLK ! LATCH ! R CLK ! ! NXM ! REQ ** FOR ! FOR DATA ! ** ! DATA ! ENB L ! ! ! ** COM/ADR ! CYCLE ! ** ! SENT ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT-I/O=212 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! 0 ! 0 ** 0 ! 0 ! 0 ** RUN ! EXECUTE ! CONTINUE ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT=100 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! RESET ! PE DETECT ** CRM PE ! DP PE ! CACHE ** 1 MSEC ! 0 ! 0 ! ! ! ENABLE ** DETECT ! DETECT ! ENABLE ** ENABLE H ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT=101 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! MODEM ** ! ! ! ! 0 ! 0 ** 0 ! 0 ! DTR ** STATE ! REMOTE ! FAULT ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT=102/103 DATA/ADR ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! DATA 28 ! DATA 29 ** DATA 30 ! DATA 31 ! DATA 32 ** DATA 33 ! DATA 34 ! DATA 35 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** Console-Register-contents Page 1-17 _________________________ WRT=104/105 DATA/ADR ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! DATA 20 ! DATA 21 ** DATA 22 ! DATA 23 ! DATA 24 ** DATA 25 ! DATA 26 ! DATA 27 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT=106/107 DATA/ADR ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! DATA 12 ! DATA 13 ** DATA 14 ! DATA 15 ! DATA 16 ** DATA 17 ! DATA 18 ! DATA 19 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT=110/111 DATA/ADR ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! DATA 4 ! DATA 5 ** DATA 6 ! DATA 7 ! DATA 8 ** DATA 9 ! DATA 10 ! DATA 11 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT=112/113 DATA/ADR ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! 0 ! 0 ** 0 ! 0 ! DATA 0 ** DATA 1 ! DATA 2 ! DATA 3 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT=114/115 DATA/ADR ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! 0 ! 0 ** 0 ! 0 ! BAD DATA ** COM/ADR ! I/O DATA ! DATA ! ! ! ** ! ! CYCLE ** CYCLE ! CYCLE ! CYCLE ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** Console-Register-contents Page 1-18 _________________________ WRT=116 ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! CSL INTERRUPT ! ! 0 ! 0 ** 0 ! 0 ! 0 ** 0 ! 0 ! THE 10 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT-I/O=200 CTY UART WRITE STATUS REGISTER(DATA BUFFER IS I/O 201) ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! HUNT MODE ! UART ** REQUEST ! RESET ! SEND ** RECEIVE ! TERMINAL ! TRANSMIT ! ! ON(SYNC) ! RESET ** TO SEND L ! ERRORS ! BREAK CHAR ** ENABLE ! READY ! ENABLE ! ! ! ** ! ! H ** ! L ! ! ****************************************************************************************************************************** RD-I/O=200 CTY UART READ STATUS REGISTER(DATA BUFFER IS I/O 201) ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! DATA SET ! SYNC ** FRAMING ! OVERRUN ! PARITY ** TRANSMITTER ! RECEIVER ! TRANSMITTER ! ! READY ! DETECT ** ERROR ! ERROR ! ERROR ** EMPTY ! READY ! READY ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** WRT-I/O=202 REMOTE UART WRITE STATUS REGISTER(DATA BUFFER IS I/O 203) ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! HUNT MODE ! UART ** REQUEST ! RESET ! SEND ** RECEIVE ! TERMINAL ! TRANSMIT ! ! ON(SYNC) ! RESET ** TO SEND L ! ERRORS ! BREAK CHAR ** ENABLE ! READY ! ENABLE ! ! ! ** ! ! H ** ! L ! ! ****************************************************************************************************************************** RD-I/O=202 REMOTE UART READ STATUS REGISTER(DATA BUFFER IS I/O 203) ****************************************************************************************************************************** ! DBUS7 ! DBUS6 ** DBUS5 ! DBUS4 ! DBUS3 ** DBUS2 ! DBUS1 ! DBUS0 ! ! ! ** ! ! ** ! ! ! ! ! ** ! ! ** ! ! ! ! DATA SET ! SYNC ** FRAMING ! OVERRUN ! PARITY ** TRANSMITTER ! RECEIVER ! TRANSMITTER ! ! READY ! DETECT ** ERROR ! ERROR ! ERROR ** EMPTY ! READY ! READY ! ! ! ** ! ! ** ! ! ! ****************************************************************************************************************************** EC-Command-Breakdown Page 1-19 ____________________ The heading is the BIT-Nr , followed by the BIT-definitions . The Bottom part links RAM-chips -- ( top for even RAM - addresses , lower part for odd ones ) *012!345!678!911*111!111!112!222*222!222!333!333*333!344!444!444*445!555!555!555*666!666!666!677*777!777!778!888*888!888!999!999* 01*234!567!890!123*456!789!012!345*678!901!234!567*890!123!456!789*012!345!678!901*234!567!890!123*456!789!012!345* --------------------------------------------------------------------------------------------------------------------------------- [ J FIELD ]*[]'![ ]![ ]![ ]*^''![ ]![ ]![ ]*[ SPECIAL # ]*'''!'''![SP # ]*[ ALU CON ]![ ]*[][! ]!''[! ]*[ ]![ ]!'''!'^'* * ! ! ! * !---! !---1 ! ! ! * ! ! ! * ! ! ! * ! ! ! * ! ! ! * ! ! ! * *[NEXT U BASE ]*TI !SKI!SPC!DIS*C !DIS!SPC!SKI*[2 PARTS**** ]* ! ![2PART]*FUN!LSC!RSC!DBM*DB[! A]! [! B]*RAM!ALU! ! C * * ! ! ! *ME !ENA!ENA!ENA*R !SEL!SEL!SEL*[ ! ! ! ]* ! ![ ! ]* ! ! !SEL*MX[!AD]! [!AD]*SRC!DST! ! R * *012!345!678!911*01C!421!421!421*ACM!421!421!421*678!911!111!111*RMP!PDM!012!345*421!421!421!421*211!421!DD1!421*421!421!SFP!PMM* * ! ! ! 01* A!000!000!000* RE! ! ! * ! 01!234!567*AUA!AIU! ! * ! ! ! * 0! !PP0! * ! !CEA!A A* * ! ! ! * L! ! ! *BYM! ! ! * ! ! ! *MLR!RVL! ! * ! ! ! * ! ! ! * ! ! R!RBR* * ! ! ! * L! ! ! *D3 ! ! ! * ! ! ! * T ! IT! ! * ! ! ! * ! !CC ! * ! !EE ! DK* * ! ! ! * ! ! ! * 8W! ! ! * ! ! ! *WIE!EDI! ! * ! ! ! * ! !LL ! * ! !NNC!C * * ! ! ! * ! ! ! *P R! ! ! * ! ! ! *R N!NE ! ! * ! ! ! * ! !KK ! * ! ! H!HP * * ! ! ! * ! ! ! *A T! ! ! * ! ! ! *TS ! P! ! * ! ! ! * ! ! ! * ! ! K!KA * * ! ! ! * ! ! ! *R ! ! ! * ! ! ! * HL!R R! ! * ! ! ! * ! !EE ! * ! ! ! R * * ! ! ! * ! ! ! * ! ! ! * ! ! ! * I ! E! ! * ! ! ! * ! !NN ! * ! ! L!R * * ! ! ! * ! ! ! *B ! ! ! * ! ! ! * F ! C! ! * ! ! ! * ! ! ! * ! ! ! B * * ! ! ! * ! ! ! *I ! ! ! * ! ! ! * T ! ! ! * ! ! ! * ! !LR ! * ! ! ! I * * ! ! ! * ! ! ! *T ! ! ! * ! ! ! * ! ! ! * ! ! ! * ! ! ! * ! ! ! T * * ! ! ! * ! ! ! * ! ! ! * ! ! ! * ! ! ! * ! ! ! * ! ! ! * ! ! ! * *<<<<<<<<< ON CRA BOARD (M8622)>>>>>>>>>>>>>>>>>*<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>* * RC0 * RC4 * RC5 A-LATCH * RC12 A-LATCH * RC14 * RC15 * RC16 * RC17 * * * * RC6 B-LATCH * RC13 B-LATCH * * * * * * LF0 * LF1 * LF2 * LF3 * LF4 * LF5 * LF6 * LF7 * --------------------------------------------------------------------------------------------------------------------------------- *<<<<<<<<< ON CRA BOARD (M8622)>>>>>>>>>>>>>>>>>*<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>* *888!888!777!777*666!666!555!555*444!444!333!333*777!777!777!777*666!666!666!666*555!555!555!555*444!444!444!444*333!333!333!333* *000!001!000!001*000!001!000!001*000!001!000!001*000!011!111!222*000!011!111!222*000!011!111!222*000!011!111!222*000!011!111!222* *135!791!135!791*135!791!135!791*135!791!135!791*246!802!468!024*246!802!468!024*246!802!468!024*246!802!468!024*246!802!468!024* *===!===!===!===*===!===!===!===*===!===!===!===*===!===!===!===*===!===!===!===*===!===!===!===*===!===!===!===*===!===!===!===* *888!888!777!777*666!666!555!555*444!444!333!333*777!777!777!777*666!666!666!666*555!555!555!555*444!444!444!444*333!333!333!333* *000!011!000!011*000!011!000!011*000!011!000!011*000!011!111!222*000!011!111!222*000!011!111!222*000!011!111!222*000!011!111!222* *246!802!246!802*246!802!246!802*246!802!246!802*357!913!579!135*357!913!579!135*357!913!579!135*357!913!579!135*357!913!579!135* --------------------------------------------------------------------------------------------------------------------------------- EC-Command-Breakdown Page 1-20 ____________________ There are also functions: 01====Read output of CRAM J field 02====Read sbr ret. reg. ( current location from last call ) Stack is 16 locs deep 03====Read current m-code instruction location. 07== NOT USED BY YOU, AS IT IS THE SELECT FORCED UP TO SELECT THE CRM BOARD MIXER INTO THE CRA BOARD MIXER FOR FUNCTIONS 10-17. 10====C RAM PARITY CHECKERS A-F(YOU CAN SPOT WHICH FIELD HOSED THE PARITY FROM THESE. ! , P,ABC,DEF! NOTE::::: THESE CHECKERS !!!!!!DO NOT!!!!!!! LOOK AT THE OUTPUTS OF THE CRA BOARD(BITS 0-35 OF THE C RAM), NOR DO THEY LOOK AT THE 'B' BUFFER LATCHES ON THE CRM BOARD. THE ONLY WAY YOU KNOW OF CRA BOARD ERRORS IS VIA THE 8080 GIVING YOU A STATUS BYTE., AND THERE IS NO EASY WAY OF BREAKING DOWN THE FIELD WITHOUT SCOPING THE CHECKERS ON PAGE CRA6. 11=THIS ALLOWS THE 8080 TO LOOP THE CRAM DATA IN 24-35 BACK TO THE KS BUS FOR DIAGNOSTIC CHECKING. THIS IS A BREAKDOWN OF THE C RAM PARITY CHECKERS, WHICH ARE AVAILABLE VIA A DIAG READ FUNCTION 10... PARITY A(BIT 30 OF FUNC 10) 36A-37A-48-49-60-61-72-73-84-85 PARITY B(BIT 31 OF FUNC 10) 38A-39A-50-51-62-63-74-75-86-87 PARITY C(BIT 32 OF FUNC 10) 40A-41A-52-53-64-65-76-77-88-89 PARITY D(BIT 33 OF FUNC 10) 42A-43A-54-55-66-67-78-79-90-91 PARITY E(BIT 34 OF FUNC 10) 44A-45A-56-57-68-69-80-81-92-93 PARITY F(BIT 35 OF FUNC 10) 46A-47A-58-59-70-71-82-83-94-95 BIT 29 OF FUNC 10 CRM BOARD HAD A ERROR(END PRODUCT OF A-F) CHAPTER 2 PROCESSOR KS10-PROCESSOR-STATUS-WORDS Page 2-2 ___________________________ HALT-STATUS-WORD STORED IN MEM LOC 0 PC STORED IN MEM LOC 1 ________________ 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *----------NOT USED---------------->*<----------------HALT STATUS CODE------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* ******** 24-35 HALT CODE DEFINITION ******** 0000 MICRCODE JUST STARTED ******** 0001 HALT INSTRUCTION EXECUTED ******** 0002 CONSOLE PROGRAM HALTED CPU ******** 0100 I/O PAGE FAILURE ******** 0101 ILLEGAL INTERRUPT INSTRUCTION ******** 0102 POINTER TO UNIBUS VECTOR IS ZERO ******** 1000 ILLEGAL MICROCODE DISPATCH ******** 1005 MICROCODE STARTUP CHECK FAILED MICROCODE-FLAGS STORED IN HALT STATUS BLOCK LOCATION X+13 IN EVENT OF PAGE FAILURE- _______________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH *<---NOT USED---------->!WREF !PICYC*CACHE!<------------------NOT USED------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH *<---------------------PAGE FAIL CODE---------------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 4 WREF WRITE REFERENCE BIT FROM PAGE MAP 5 PICYC PI CYCLE 6 CACHE LOOK IN CACHE BIT FROM PAGE MAP 18-35 PAGE FAIL CODE-SPECIFIES THE OPERATION FOR WHICH THE PAGE FAIL CODE OCCURRED 000000 SIMPLE INSTRUCTIONS 000001 BLT IN PROGRESS 400002 MAP IN PROGRESS 000003 MOVE STRING SOURCE IN PROGRESS 000004 MOVE STRING FILL IN PROGRESS 000005 MOVE STRING DESTINATION IN PROGRESS 000006 FILLING DESTINATION 000007 EDIT SOURCE 000010 EDIT DESTINATION 000011 CONVERTING DECIMAL TO BINARY 000012 COMPARING DESTINATION KS10-PROCESSOR-STATUS-WORDS Page 2-3 ___________________________ VMA VIRTUAL MEM ADDRESS AND FLAGS -STORED IN LOCATION X+20 OF HALT STATUS BLOCK ___ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH *USER ! !FETCH*R CYC!W TST!W CYC* !-CACH!PHYS *VMA P!VMA I!WRU C!VEC B!BYTE !<---PHYS ADDRESS------>* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH *<--------VIRTUAL ADDRESS(BIT 8=0) OR PHYSICAL ADDRESS(BIT 8=1)-------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 0 USER USER MODE 1 NOT USED 2 FETCH INSTRUCTION FETCH 3 R CYC READ CYCLE 4 W TST WRITE TEST 5 W CYC WRITE CYCLE 6 NOT USED 7 -CACH DO NOT LOOK IN CACHE (REFERENCE INDEX TO FIND MORE INFORMATION ON THE HALT STATUS BLOCK) 8 PHYS PHYSICAL REFERENCE 9 VMA PREVIOUS 10 VMA I/O 11 WRU CYCLE 12 VECTOR BYTE 13 BYTE I/O BYTE INSTRUCTION 14-17 BITS 14-17 OF A PHYSICAL ADDRESS(0'S) 18-35 BITS 18-35 OF ADDRESS PC-WORD STORED BY JSR AND OTHER INSTRUCTIONS IN MEM LOCATIONS OR AC'S _______ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH *OVFL ! CARRY *FLT !FPD !USER *USER !<--NOT USED* TRAP !FLT *NO !<----------NOT USED----------* * ! 0 ! 1 *OVFL ! ! *IOT ! * 2 ! 1 !UFLO *DIV ! * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH *<----------------------------------PROGRAM COUNTER-------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 0 OVFL OVERFLOW 1 CARRY 0 2 CARRY 1 3 FLTOVFL FLOATING OVERFLOW 4 FPD FIRST PART DONE 5 USER USER MODE 6 USER IOT(ALSO PCU) 9 TRAP 2 10 TRAP 1 11 FLTUFLO FLOATING UNDERFLOW 12 NODIV NO DIVIDE 18-35 PROGRAM COUNTER KS10-PROCESSOR-STATUS-WORDS Page 2-4 ___________________________ PAGE-FAIL-WORD(or-MAP-AC) -STORED IN LOCATION 500 OF UPT ON A CPU PAGE PAIL TRAP _________________________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH *USER !<--PAGE FAIL CODE OR-------->* ! PT !PAGED<-----NOT USED--------------->!<----ADDRESS---------->* *ADDR ! 0 !TV *WRTN !WRTL !WREF * !CASH !REF ! * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH *<----------VIRTUAL ADDRESS(PYSICAL ADDRESS FOR MAP IF BIT 2=1)-------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 0 USER ADDRESS 2-5 MAP AC(BIT 1=0) 2 TRANSLATION VALID 3 WRITTEN (TOPS 20 ONLY ) 4 WRITEABLE (TOPS 20 ONLY ) 5 WRITE REFERENCE ******** 2-5 PAGE FAIL CODE(BIT 1=1) ******** 2 20=IO INSTRUCTION SELECTED A NON EXISTENT DEVICE OR REGISTER(BITS 14-35=THE IO ADDRESS) ******** 25=PAGE TABLE PARITY ERROR ******** 36=HARD MEMORY ERROR ******** 37=NXM ******** 7 PAGE CACHE-ABLE ******** 8 PAGED REFERENCE Paging Page 2-5 ______ ************************ ****************************** KS10 UPT TOPS20 PAGING KS10 EPT TOPS20 PAGING ************************ ****************************** 0-420 NOT USED 0-41 NOT USED 421 USER ARITHMETIC OVFL TRAP INST 42-57 STANDARD PRIORITY INTERRUPT INST 422 USER STACK OVF TRAP INST 60-77 NOT USED 423 USER TRAP 3 TRAP INST 100-117 VECTOR INTERRUPT TABLE POINTERS 424 FLAGS 1 MUUO OP-AC 120-420 NOT USED 425 MUUO OLD PC 421 EXEC ARITHMETIC OVF TRAP INST 426 E OF MUUO 422 EXEC STACK OVF TRAP INST 427 MUUO PROCESS CONTEXT WORD 423 EXEC TRAP 3 TRAP INST 430 KERNAL NO TRAP MUUO NEW PC WORD 424-537 NOT USED 431 KERNAL TRAP MUUO NEW PC WORD 540 EXEC SEC 0 PTR 432 SUPERVISOR NO TRAP MUUO NEW PC WORD 433 SUPERVISOR TRAP MUUO NEW PC WORD 434 CONCEALED NO TRAP MUUO NEW PC WORD 435 CONCEALED TRAP MUUO NEW PC WORD 436-477 NOT USED 500 PAGE FAIL WORD 541-777 NOT USED 501 PAGE FAIL FLAGS 502 PAGE FAIL OLD PC 503 PAGE FAIL NEW PC 504-537 NOT USED 540 USER SEC 0 PTR 541-777 NOT USED ************************ ****************************** KS10 UPT TOPS10 PAGING KS10 EPT TOPS10 PAGING ************************ ****************************** 0-377L USER PAGE 0-776 0-41 NOT USED 0-377R USER PAGE 1-777 42-57 STANDARD PRIORITY INTERRUPT INST 400-417L EXEC PAGE 340-376 60-77 NOT USED 400-417R EXEC PAGE 341-377 100-117 VECTOR INTERRUPT TABLE POINTERS 420 ADDRESS OF LUUO BLOCK 120-177 NOT USED 421 USER ARITHMETIC OVF 200-377L EXEC PAGE 400-776 422 USER STACK OVF TRAP INST 200-377R EXEC PAGE 401-777 423 USER TRAP 3 TRAP INST 400-420 NOT USED 424 MUUO STORED HERE 421 EXEC ARITHMETIC OVF TRAP INST 425 PC WORD OF MUUO STORED HERE 422 EXEC STACK OVF TRAP INST 426 PROCESS CONTEXT WORD STORED HERE 423 EXEC TRAP 3 TRAP INST 427 NOT USED 424-577 NOT USED 430 KERNAL NO TRAP MUUO NEW PC WORD 600-757L EXEC PAGE 0-336 431 KERNAL TRAP MUUO NEW PC WORD 600-757R EXEC PAGE 1-337 432 SUPERVISOR NO TRAP MUUO NEW PC WORD 760-777 NOT USED 433 SUPERVISOR TRAP MUUO NEW PC WORD 434 CONCEALED NO TRAP MUUO NEW PC WORD 435 CONCEALED TRAP MUUO NEW PC WORD 436-477 NOT USED 500 EXEC OR USER PAGE FAIL WORD STORED HERE 501 EXEC OR USER OLD PC WORD STORED HERE 502 PAGE FAIL NEW PC WORD 503-777 NOT USED KS10-I/O-INSTRUCTION-FORMAT Page 2-6 ___________________________ IN THE KS10 THE IO INSTRUCTION FORMAT IS THE SAME AS A TRADITIONAL PDP10 INSTRUCTION FORMAT...AS FOLLOWS 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH *<-------INSTRUCTION OP CODE(700-777 OCTAL)---------->*<--AC FIELD(00-17)---->! I !<---INDEX REGISTER---->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH *<---------------------Y(ADDRESS)-------------------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* I=INDIRECT ADDRESSING BIT INDEX REGISTER 00-17 *Note: The AC field is used as an op-code extension for theAPR I/O instructions . KS10-IO-INSTRUCTION-OP-CODES-IN-OCTAL _____________________________________ 0 1 2 3 4 5 6 7 ========================================================================== 700 APR0 APR1 APR2 - UMOVE UMOVEM - - ========================================================================== 710 TIOE TION RDIO WRIO BSIO BCIO - - ========================================================================== 720 TIOEB TIONB RDIOB WRIOB BSIOB BCIOB - - ========================================================================== 730 ========================================================================== 740 ========================================================================== 750 ========================================================================== 760 ========================================================================== 770 ========================================================================== KS10-APR-IO-INSTRUCTIONS-AC-FIELD-ASSIGNMENTS _____________________________________________ AC 700 701 702 00 APRID - RDSPB 04 - RDUBR RDCSB 10 - CLRPT RDPUR 14 - WRUBR RDCSTM 20 WRAPR WREBR RDTIME 24 RDAPR RDEBR RDINT 30 - - RDHSB 34 - - - 40 - - WRSPB 44 - - WRCSB 50 - - WRPUR 54 - - WRCSTM 60 WRPI - WRTIME 64 RDPI - WRINT 70 - - WRHSB 74 - - - INTERNAL-REGISTER-BIT-FORMATS Page 2-7 _____________________________ APRID=700000 ____________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<-------MICROCODE OPTIONS--------------------------->*<--------------------MICROCODE VERSION NUMBER------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<-HDWR OPTIONS-->*<--------------------PROCESSOR SERIAL NUMBER-------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* WRAPR(CONO-APR)=700200 ______________________ 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* E * ! !EN *DIS !CLR !SET * !80INT!PWRF *NXM !HERR !SERR *ITIM !KSINT!INTRQ*PI4 !PI2 !PI1 * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 20 EN ENABLE CONDITIONS SPECIFIED BY BITS 26-31 TO CAUSE INTERRUPTS 21 DIS Disable interrupts for conditions selected by bits 26-31 22 CLR Clear flags indicated by bits 26-31 23 SET SET FLAGS SPECIFIED BY 26-31 25 80INT INTERRUPT 8080 FROM KS 26 PWRF POWER FAIL 27 NXM NON-EXISTENT MEMORY ERROR 28 HERR HARD MEMORY ERROR(UNCORRECTABLE) 29 SERR SOFT MEM ERROR (CORRECTABLE) 30 ITIM INTERVAL TIMER 31 KSINT INTERRUPT KS FROM 8080 32 INTRQ GENERATE INTERRUPT REQUEST 33-35 PI PRIORITY INTERRUPT ASSIGNMENT RDAPR(CONI-APR)=70024 STORE THE APR STATUS IN THE WORD ADDRESSED BY E _____________________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<---------------------NOT USED---------------->*PWRFE*NXME !HERRE!SERRE*ITIME!8080E!<----NOT USED--------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<--------NOT USED----------------------------->!PWRF *NXM !HERR !SERR *TDONE!80INT!INTRQ*PI 4 !PI 2 !PI 1 * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* BITS 8,9,10,11,12,13=SELECTED FLAGS ENABLED 13 8080E 8080 INTERRUPT enabled 26 PWRF POWER FAIL *27 NXM NON EXISTENT MEMORY *28 HERR HARD MEM ERROR 29 SERR SOFT MEM ERROR(CORRECTED DATA RETURNED ON BUS) *NOTE: PAGE FAIL OCCURS IF ERROR IS RESULT 30 TDONE INTERVAL TIMER DONE OF CPU MEMORY REQUEST 31 80INT 8080 INTERRUPT NXM ALSO SETS IN UNIBUS DEVICE IF ERROR 32 INTRQ INTERRUPT REQUEST results from UNIBUS NPR REQUEST 33-35 PIL PRIORITY INTERRUPT LEVEL INTERNAL-REGISTER-BIT-FORMATS Page 2-8 _____________________________ WRPI(CONO-PI)=700600 ____________________ 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* E *<-----NOT USED ON KS->!DROP !CLEAR*REQ !TURN !CHAN *TURN !SYS !<-------SELECT CHANNEL------------------>* * !INT !SYS *INT !ON !OFF *OFF !ON ! 1 * 2 ! 3 ! 4 * 5 ! 6 ! 7 * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 22 DROP PROGRAM REQUESTS ON SELECTED CHANNELS 23 CLEAR PI SYSTEM 24 INITIATE INTERRUPTS ON SELECTED CHANNELS 25/26 TURN SELECTED CHANNELS ON OR OFF 27/28 TURN THE PI SYSTEM ON OR OFF 29-35 SELECT CHANNELS FOR BITS 22,24,25,26 RDPI=700640 ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<---------------------NOT USED---------------------------------->!<-----PROGRAM REQUESTS------------------>* * ! 1 * 2 ! 3 ! 4 * 5 ! 6 ! 7 * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<--NOT USED----->*PI IN PROGRESS(INTERRUPTS HOLDING-------->!SYS !<---------ACTICE CHANNELS ON----------->* * * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 !ON ! 1 * 2 ! 3 ! 4 * 5 ! 6 ! 7 * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RDUBR=70104 ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) * 1 ! 0 ! 1 *<--NOT USED----->*CURR AC BLK *PREV AC BLOCK *<-------------NOT implemented------* * * *4 !2 !1 * 4 ! 2 ! 1 * * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *<-----------NOT implemented------------->!<---USER BASE REGISTER(PHYSICAL PAGE #(BITS 16-26))------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* BITS 0,2 set to a one so that word may be directly used by WRUBR UBR contains the physical page number of the user process table WRUBR=70114 LOAD THE UBR WITH THE WORD AT E ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *LOAD ! 0 !LOAD *<---NOT USED---->*<--CURR AC BLK-->*<--PREV AC BLK-->*<--------NOT implemented---------->* *ACBLK! !UBR * * 4 ! 2 ! 1 * 4 ! 2 ! 1 * * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<---NOT implemented--------------------->!<-------USER BASE REGISTER(PHYSICAL PAGE # OF UPT(BITS 16-26))-->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* INTERNAL-REGISTER-BIT-FORMATS Page 2-9 _____________________________ CLRPT=70110 ___________ 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* E *<------------------VIRTUAL ADDRESS TO CLEAR IN HARDWARE PAGE TABLE---------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* This instruction clears the hardware page table so that the next reference to word at E will cause page refill cycle. Note: There is one entry only for any virtual page. Clearing the map information clears both EXEC and USER mapping. WREBR=70120 ___________ 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* E * *KL10 !TRAP ! * !<----EXEC BASE REGISTER(PHYSICAL PAGE # OF EPT(BITS 16-26)------>* * ! ! *PAGE !EN ! * ! * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 21 KL PAGING MODE 22 TRAP ENABLE RDEBR=70124 STORE THE VALUE GIVEN BY THE PREVIOUS WREBR INTO THE EFFECTIVE ADDRESS ___________ 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) * ! ! *KL10 !TRAP ! * !<-------EXEC BASE REGISTER(PHYSICAL PAGE # OF EPT(BITS 16-26))-->* * ! ! *PAGE !EN ! * ! * *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* WRSPB=70240 WRITE SPT(SHARED POINTER TABLE BASE REGISTER)-LOAD THE WORD AT E INTO THE SPT BASE REGISTER ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<--------------------------NOT IMPLEMENTED---------------------------------------->!<-----SPT--------------* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<--------------SPT BASE REGISTER-------------------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RDSPB=70200 READ SPT BASE REGISTER STORE THE SPT BASE REGISTER AT E ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<------------------------NOT IMPLEMENTED------------------------------------------>!<-------SPT------------* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<------------SHARED POINTER BASE REGISTER----------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* INTERNAL-REGISTER-BIT-FORMATS Page 2-10 _____________________________ WRCSB=70244 WRITE=CORE STATUS TABLE BASE REGISTER LOAD THE CST BASE REGISTER WITH THE WORD AT E ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<-------------------------------------NOT USED------------------------------------>!<-----CST-------------* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<---------CORE STATUS TABLE BASE REGISTER (BITS 16-35)---------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RDCSB=70204 READ CORE STATUS TABLE BASE REGISTER ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<------------------------NOT USED------------------------------------------------->!<-------CST------------* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<----------------CORE STATUS TABLE BASE REGISTER---------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* WRPUR=70250 WRITE PROCESS USE REGISTER ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *<------------------------PROCESS USE REGISTER------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<--------------------------PROCESS USE REGISTER----------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *Note: Load the process use register from E . The PUR contains the ager ( AGE register) in the left few bits. The bits containing the ager are cleared by anding the CST entry with the CST mask , the entire PUR is or'ed with the CST entry. RDPUR=70210 STORE THE PUR AT E ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<--------------------------------PROCESS USE REGISTER----------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<---------------------------------PROCESS USE REGISTER---------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* INTERNAL-REGISTER-BIT-FORMATS Page 2-11 _____________________________ WRCSTM=70254 WRITE THE CST MASK REGISTER ____________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<------------CORE STATUS TABLE MASK REGISTER-------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<---------------------------CORE STATUS TABLE MASK REGISTER----------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* Note: Load the CST mask register from E. The CST mask register should contain a 0 for every bit in the ager and a ONE BIT in all other bit positions. RDCSTM=70214 ____________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<-----------------------CST MASK REGISTER----------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<-------------------------CST MASK REGISTER--------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* WRTIME=70260 Write the TIME BASE ____________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E+1) *SIGN !<------------HIGH ORDER TIME BASE------------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E+1) *<--------------------HIGH ORDER TIME BASE----------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *SIGN !<-----------------LOW ORDER TIME BASE--------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<-----LOW ORDER TIME BASE--------->*<-----------------------------------NOT USED-------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* SIGN SIGN BIT 0=positive 1=negative TIME BASE in MILLESECONDS Note: Load the double word at E and E+1 into the TIME BASE. The TIME BASE counts up at 4.09 MHz. INTERNAL-REGISTER-BIT-FORMATS Page 2-12 _____________________________ RDTIME=70220 ____________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E+1) *SIGN !<--------------------------HIGH ORDER TIMBASE(MILLISECONDS0----------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E+1) *<------------------HIGH ORDER TIMEBASE(MILLISECONDS)------------------------------------------------------>* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *< 0 >!<---------------------LOW ORDER TIMEBASE------------------------------------------------------------>* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) **<-----------TIME BASE FRACTION---------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* Note: Store the TIME BASE at E and E+1 WRINT=70264 ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<------------INTERVAL TIMER------------------------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<--INTERVAL TIMER----------------->*>-------------------NOT USED------------------------------------------>* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* Note: Load the INTERVAL TIMER period register with the word at E ( units are milliseconds ). RDINT=70224 READ THE INTERVAL REGISTER ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *<-----------------------------INTERVAL TIMER-------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<-----INTERVAL TIMER-------------->*<-------------------------NOT USED------------------------------------>* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* Note: Store the current value of the INTERVAL register at E. Returns the interval loaded by WRINT , does not change with time. INTERNAL-REGISTER-BIT-FORMATS Page 2-13 _____________________________ WRHSB=70270 WRITE HALT STATUS BLOCK ADDRESS ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *SIGN !<---------------------------NOT USED---------------------------------------->!<---HSB ADDRESS------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<---------------HSB ADDRESS------------------------------------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* Note: Use the word at E as the HALT-Status block address. If the SIGN bit is negative or zero no Halt Status will be stored. If positive the internal processor status will be stored. The status consists of the 16 2901 registers , VMA , SC and FE. The programmer should allow 32 words for this block. The m-code initially sets the address to 376000. TOPS20 changes it to 400 , TOPS10 changes it to 424. RDHSB=70230 READ THE HALT STATUS BLOCK ADDRESS ___________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* LH(E) *SIGN !<---------------NOT USED---------------------------------------------------->!<-------HSB ADDRESS--->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RH(E) *<------------------------------HALT STATUS BLOCK ADDRESS-------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* Note: Store the current value of the HALT Status block ADDRESS at E. EXTERNAL-REGISTERS Page 2-14 __________________ To access an external register , the external IO instructions generate an extended 30 bit address , which is used as an IO address. Bits 14-17 are IO controller numbers and bits 18-35 are used as the register address. An extended address is required to address controllers other than zero. i.e. the programmer must use indexing or indirection to yield the desired effective address. For example , to write the first control status register in the RH11 with a write function code of 61 , assuming the RH11 is on the first controller , the programmer could either 1/WRTIO AC,0(XR) where XR(index register)contains 1,,776700 and AC contains 61 or 2/WRTIO AC,@DRPCS1 where the location DRPCS1 contains 1,776700 and AC contains 61 or 3/WRTIO AC,776700(XR) where XR contains the CONT # in BITS 14-17 an addressing scheme such as this could be useful for using common code amoung different IO controllers. Byte instructions will transfer only 8 bits of data from the LSB's of AC. Currently there are two slots allocated for IO controllers. These are now UNIBUS ADAPTER modules. The controller numbers are hardwired on the backplane. SLOT I/O CONTROLLER# 19 1 16 3 EXTERNAL-REGISTERS-BIT-FORMATS Page 2-15 ______________________________ UBA-PAGING-RAM IO ADDRESS 763000-763077 ______________ WRIO(713)-AC,7630XX ___________________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *<-----------------------------------------------NOT USED-------------------------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *F RPW!EN16 !F M E!VALID!<-----NOT USED->!<-------PAGE BITS---10ADR 16 THRU 26----------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RDIO(712)-AC,7630XX ___________________ 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *<----!-----!-----!-----!RAM P!F RPW*EN16 !F M E !VALID*R P V!-----!-----*-----!-----!-----*-----!<-----PAGE *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* -RAM BITS 10 ADR 16-26------------------------------->*<----------NOT USED--------------------------------->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RAM P RAM PARITY BIT F RPW FORCE READ PAUSE WRITE FOR EVEN/ODD MEM WRITES EN 16 DISABLE UPPER 2 BITS ON UNIBUS TRANSFERS F M E Fast Mode Enable for 36 BIT FAST MODE TRANSFERS VALID PAGE IS VALID R P V PAGING RAM PARITY valid EXTERNAL-REGISTERS-BIT-FORMATS Page 2-16 ______________________________ UBA-STATUS-REGISTER IO ADDRESS 763100 ___________________ WRIO(713) _________ 18 19 20 * 21 22 23 * 24 25 26 * 27 ! 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *C TIM!C BAD!C PAR*C NED!<-------------NOT USED ON WRT----->!D XFR!UINIT*<----PIH-------->*<------PIL------>* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* RDIO(712) _________ 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* * TIM! BAD! PAR* NED! *INT H!INT L!PWR L* !DXFR ! *<----PIH-------->*<---------PIL--->* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 R/W TIM UNIBUS ARBITRATOR TIMEOUT-NO SACK IN 5 MICRO SEC-CP ADDRESSED NON EXISTENT DEV REG OR DEV ADDRESSED NON EXISTENT MEMORY 1 CLEARS THE BIT 19 R/W BAD BAD MEM DATA ON NPR TRANSFER-MASTER WILL TIME OUT ON BAD MEM DATA IF 28 SET-WRT CLEARS THE BIT 20 R/W PAR KS10 BUS PARITY ERROR-WRITE CLEARS THE BIT 21 R/W NED CPU ADDRESSED NON EXISTENT DEVICE-WRT CLEARS THE BIT 24 RONLY INT H INTERRUPT REQUEST ON BR6 OR BR7 25 RONLY INT L INTERRUPT REQUEST ON BR5 OR BR4 26 RONLY PWR L AC LOW OR DC LOW-CLEARED ON REGISTER WRITE 28 R/W DXFR DISABLE TRANSFER ON UNCORRECTABLE DATA 29 WONLY UINIT ISSUE UNIBUS INIT 30-32 R/W PIH PI LEVEL OF BR6,BR7 33-35 R/W PIL PI LEVEL OF BR4,BR5 UBA-MAINTENANCE-REG IO ADDRESS 763101 ___________________ 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *<------------------------------------NOT USED------------------------------------------------->!S M B!C N A* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* WONLY BIT 34 S M B Spare Maintenance Bit WONLY BIT 35 C N A Change NPR address EXTERNAL-REGISTERS-BIT-FORMATS Page 2-17 ______________________________ MEMORY-STATUS-REGISTER IO ADDRESS 100000 ______________________ THE MEMORY WILL HOLD THE ERROR ADDRESS,THE ECC CODE AND THE TYPE OF ERROR FOR THE FIRST ERROR DETECTED. BIT00,THE ERROR HOLD BIT, MUST BE CLEARED TO ALLOW THE MEMORY TO CONTINUE AND THE CAPTURE THE NEXT ERROR IN THE STATUS REGISTER. 00 01 02 * 03 04 05 * 06 07 08 * 09 10 11 * 12 13 14 * 15 16 17 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *HOLD !BAD D!R ERR*P ERR!ECCON! CP * C40 ! C20 ! C10 * C04 ! C02 ! C01 *PFAIL! 0 !ADR14*ADR15!ADR16!ADR17* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 18 19 20 * 21 22 23 * 24 25 26 * 27 28 29 * 30 31 32 * 33 34 35 *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* *ADR18!ADR19!ADR20*ADR21!ADR22!ADR23*ADR24!ADR25!ADR26*ADR27!ADR28!ADR29*ADR30!ADR31!ADR32*ADR33!ADR34!ADR35* *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----* 00 HOLD MMC5 ERR HOLD SET ON ERROR CONDITION DETECTED BY CONTROLLER-CLEARED WHEN WRITTEN WITH A 1 01 BAD D MMC4 UNCOR ERR HOLD SET SAYS ERROR IN REG WAS UNCORRECTABLE 02 R ERR MMC9 REF ERR REFRESH ERR SET 5.5 USEC AFTER COM/ADR IF NO DATA RECIEVED.CLEARS ANY CYCLE IN PROGRESS AND REFRESHES THE MOS ARRAYS.CLEARED WHEN WRITTEN WITH A 1 OR MR. 03 P ERR MMC7 PARITY ERR MMC RECIEVED A PARITY ERR ON THE KS10 BUS. SET BY WRITING 1 TO BIT 3;CLEARED BY WRITING 0 TO BIT 3 OR MR. 04 ECCON MMC3 ECC ON THE ERROR CORRECTION LOGIC IS ENABLED WHEN ON.WHEN OFF ERRORS WILL STILL BE DETECTED BUT NO CORRECTIONS MADE.TURNED ON BY MR ,turned off by IO WRITE TO BIT 35 OF THE STATUS REG 05 CP MMC4 ERR CP PARITY BIT OF THE CORRECTION CODE 06 C40 MMC4 ERR C40 CORR CODE BIT C40 07 C20 MMC4 ERR C20 CORRCTION CODE BIT C20 08 C10 MMC4 ERR C10 CORR CODE BIT C10 09 C04 MMC4 ERR C04 CORR CODE C04 10 C02 MMC4 ERR C02 CORR CODE BIT C02 11 C01 MMC4 ERR CO1 CORR CODE BIT C01 12 P FAIL MMC5 POWER FAILED SET IF MEM HAS LOST POWER OR BATTERY BACKUP FAILED.CLEARED WHEN WRITTEN WITH A 1. 13 0 UNUSED ALWAYS UNASSERTED 14-35 ADRXX MMC8 ERR ADR14-35 BITS 14-35 OF THE ERROR ADDRESS REGISTER. IADDRESS BITS ------------- 14-16 SELECT CONTROLLER 17-19 SELECT ARRAY BOARD 20-21 SELECTS ONE OF FOUR WORDS ON THE SELECTED BOARD