TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS042A - DECEMBER 1997 - REVISED FEBRUARY 1998

features

• Single-Chip With Eight-Channel Physical-Layer (PHY) Interfaces in One Package for Internetworking Applications
• Each PHY is Full-Duplex Capable for Simultaneous Transmit and Receive
• Compliant With IEEE Std 802.3 10BASE-T Specification
• Integrated Filters on Both Receive and Transmit Circuits
  • No External Filters Are Required
  • Meets IEEE Std 802.3 (Section 14.3) Electrical Requirements
• Implements IEEE Std 802.3 Autonegotiation to Establish the Highest Common Protocol
• Digital Signal Processor (DSP)-Based Digital Phase-Locked Loop (PLL)
• Loopback Mode for Test Operations
• Integrated Manchester Encoding/Decoding
• Receive-Clock Regeneration for All Input Channels Using Digital PLL
• FIFOs Accommodate 8x IEEE Limit on Per-Channel-Pair Frequency Mismatch Across All Eight Channels (IEEE Std 802.3, Sec 7.3.2)
• Intelligent Squelch With Selectable Threshold
• Link-Pulse Detection and Autonegotiation
• Intelligent Rejection of MLT-3 Encoded Data
• Transmit Pulse Shaping Reduces Electromagnetic Interference (EMI)
• Clock Synchronization Between Channels
• Collision Detection
• Built-In Jabber Detection
• Automatic Reversed-Polarity Detection and Correction
• Sufficient Current Drive to Directly Connect LED Status Indicators
• CMOS Technology Enables Low Power Consumption
• 3.3-V Operation
• IEEE Std 1149.1 (JTAG) Test-Access Port (TAP)
• Direct Drive to Network Coupling Magnetics
• Packaged in 120-Pin Plastic Quad Flatpack

  IEEE Std 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture Ethernet is a trademark of Xerox Corporation.

description

The TNETE2008 OctalPHY is a physical-layer (PHY) interface device for up to eight 10BASE-T networks using a multiplexed medium access controller (MAC) interface compatible with a TNETX3270 switch device or equivalent. A digital signal processor (DSP) phase-locked loop (PLL) is used on each channel to recover data. Integrated wave shaping of the output eliminates the need for filters to meet electronic interference (EMI) testing. DSP wave-shaping techniques used internally reduce the required number of external components to a coupling transformer, four resistors, and a capacitor per channel. The multiplexed host interface reduces the number of terminals required to connect eight networks to eight MAC engines, allowing the use of a single package.

The TNETE2008 operation is fully automatic. It can be taken from reset to full operation without parameter downloads or interaction with a host central processing unit (CPU). Some mode terminals affect all of the ports, such as looping back transmit data to the receive path, powering down the PHY, and setting the receiver threshold. There are no management interfaces or internal registers on this device. A directly driven LED matrix provides Ethernet^TM status indicators, i.e., link, activity, collision, and duplex. The TNETE2008 produces and receives IEEE Std 802.3-compliant waveforms when coupled to the network with a suitable transformer. The TNETE2008 also incorporates a JTAG-compliant test port.

The TNETE2008 provides PHY interface functions for up to eight 10BASE-T network ports as shown in Figure 1.

A typical application with external components is shown in Figure 2.

Figure 1. TNETE2008 OctalPHY Architecture

Figure 2. TNETE2008 External Components

View more information about generic part numbers:TNETE2008

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