ThunderLAN^TM TNETE110PM PCI ETHERNET^TM CONTROLLER SINGLE-CHIP 10 BASE-T

SPWS029 - SEPTEMBER 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Single-Chip Ethernet^TM Adapter for the Peripheral Component Interconnect (PCI) Local Bus
  • 32-Bit PCI Glueless Host Interface
  • Compliant With PCI Local-Bus Specification (Revision 2.1)
  • 33-MHz Operation
  • 3-V or 5-V I/O Operation
  • Adaptive Performance Optimization^TM (APO) for Highest Available PCI Bandwidth
  • High-Performance Bus Master Architecture With Byte-Aligning Direct Memory Access (DMA) Controller for Low Host CPU and Bus Utilization
  • Plug-and-Play Compatible
• Supports 32-Bit Data Streaming on PCI Bus
  • Time Division Multiplexed SRAM
  • 2-Gbps Internal Bandwidth
• Driver Compatible With All Previous ThunderLAN Components
• Switched-Ethernet Compatible
• Full-Duplex Compatible
  • Independent Transmit and Receive Channels
  • Two Transmit Channels for Demand Priority
• No On-Board Memory Required
• Auto-Negotiation (N-Way) Compatible
• Supports the Card Bus CIS Pointer Register
• Early-Receive-Interrupt Count Register
• Hardware Statistics Registers for Management-Information Base (MIB)
• Integrated 10 Base-T, and 10 Base-5 Attachment Unit Interface (AUI) Physical Layer Interface
  • Single-Chip IEEE 802.3 and Blue Book Ethernet-Compliant Solution
  • DSP-Based Digital Phase-Locked Loop
  • Smart Squelch Allows for Transparent Link Testing
  • Transmission Waveshaping
  • Autopolarity (Reverse Polarity Correction)
  • External/Internal Loopback Including Twisted Pair and AUI
  • 10 Base-2 Supported Via AUI Interface
• Magic Packet^TM Remote Wake-Up Scheme
• Microsoft^TM Advanced Power Management
  • PCI Specification Compatible for Low Power/Sleep Mode
  • Advanced Configuration and Power Interface (ACPI)
• Low-Power CMOS Technology
  • Green PC Compatible
• EEPROM Interface Supports Jumperless Design and Autoconfiguration
• DMTF (Desktop Management Task Force) Compatible
• IEEE Standard 1149.1 Test-Access Port (JTAG)
• 144-Pin Thin Quad Flat Packages and Quad Flat Packages (PCM and PGE Suffix)

  The PCI Local-Bus Specification, Revision 2.1 should be used as a reference with this document.

  IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture

  ThunderLAN and Adaptive Performance Optimization are trademarks of Texas Instruments Incorporated.

  Ethernet is a trademark of Xerox Corporation.

  Microsoft is a trademark of Microsoft Corporation.

  Magic Packet is a trademark of Advanced Micro Devices Corporation.

description

ThunderLAN is a high-speed networking architecture that provides a complete PCI-to-10 Base-T/AUI Ethernet solution. The TNETE110PM, one implementation of the ThunderLAN architecture (see Figure 1), is an intelligent-protocol network interface. The ThunderLAN SRAM FIFO-based architecture eliminates the need for external memory and offers a single-chip glueless PCI-to-10 Base-T/AUI (IEEE 802.3) solution with an on-board physical layer interface.

The glueless PCI interface supports 32-bit streaming, operates at speeds up to 33 MHz, and is capable of internal data-transfer rates up to 2 Gbps, taking full advantage of all available PCI bandwidth. The TNETE110PM offers jumperless autoconfiguration using PCI configuration read/write cycles. Customizable configuration registers, which can be autoloaded from an external serial EEPROM, allow designers of TNETE110PM-based systems to give their systems a unique identification code. The TNETE110PM PCI interface, developed in conjunction with other leaders in the semiconductor and computer industries, has been vigorously tested on multiple platforms to ensure compatibility across a wide array of available PCI products. In addition, the ThunderLAN drivers and ThunderLAN architecture use TI's patented Adaptive Performance Optimization (APO) technology to adjust critical parameters for minimum latency dynamically, minimum host CPU utilization, and maximum system performance. This technology ensures that the maximum capabilities of the PCI interface are used by automatically tuning the adapter to the specific system in which it is operating.

An intelligent protocol handler (PH) implements the serial protocols of the network. The PH is designed for minimum overhead related to multiple protocols, using common state machines to implement 95% of the total protocol handler. On transmit, the PH serializes data, adds framing and cyclic redundancy check (CRC) fields, and interfaces to the network physical layer (PHY) chip. On receive, it provides address recognition, CRC and error-checking, frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by way of circular-buffer FIFOs in the FIFO SRAM.

Compliant with IEEE Standard 1149.1, the TNETE110PM provides a five-pin test-access port that is used for boundary-scan testing.

The TNETE110PM is available in a 144-pin thin quad flat package (TQFP) and quad flat package (QFP).

View more information about generic part numbers:TNETE110PM

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
Trademarks, Important Notice!