ThunderLAN^TM TNETE100PM PCI ETHERNET^TM CONTROLLER WITH POWER MANAGEMENT SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS026 - OCTOBER 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Single-Chip Ethernet^TM Controller for the Peripheral Component Interconnect (PCI) Local Bus
  • 32-Bit PCI Glueless Host Interface
  • Compliant With PCI Local-Bus Specification (Revision 2.1)
  • 0-MHz to 33-MHz Operation
  • 3-V or 5-V I/O Operation
  • Adaptive Performance Optimization^TM (APO) by Texas Instruments (TI^TM) for Highest Available PCI Bandwidth
  • High-Performance Bus Master Architecture With Byte-Aligning Direct Memory Access (DMA) Controller for Low Host CPU and Bus Utilization
  • Plug-and-Play Compatible
• Supports 32-Bit Data Streaming on PCI Bus
  • Time-Division Multiplexed Static Random-Access Memory (SRAM)
  • 2-Gbps Internal Bandwidth
• Driver Compatible With All Previous ThunderLAN^TM Components
• Switched-Ethernet Compatible
• Full-Duplex Compatible
  • Independent Transmit and Receive Channels
  • Two Transmit Channels for Demand Priority
• Supports Multiple Protocols With a Single Driver Suite Optimized Shared Interrupts
• No On-Board Memory Required
• Auto-Negotiation (N-Way) Compatible
• Multimedia-Ready Architecture
• Supports the Card-Bus Card Information Structure (CIS) Pointer Register
• Early-Receive-Interrupt Count Register
• EEPROM Interface Supports Jumperless Design and Autoconfiguration
• Hardware Statistics Registers for Management-Information Base (MIB)
• Desktop Management Task Force (DMTF) Compatible
• Integrated 10 Base-T, and 10 Base-5 Attachment Unit Interface (AUI) Physical Layer Interface
  • Single-Chip IEEE 802.3 and Blue Book Ethernet-Compliant Solution
  • DSP-Based Digital Phase-Locked Loop
  • Smart Squelch Allows for Transparent Link Testing
  • Transmission Waveshaping
  • Autopolarity (Reverse Polarity Correction)
  • External/Internal Loopback Including Twisted Pair and AUI
  • 10 Base-2 Supported Through AUI Interface
• Media-Independent Interface (MII) for Connecting 100-Mbps External Transceivers
  • Compliant MII for IEEE 802.3u Transceivers
  • Supports 100 Base-TX, 100 Base-T4, 100 Base-FX
  • Super Set Supports IEEE 802.12 Transceivers
  • Supports Ethernet and Token-Ring Framing Formats for 100VG-AnyLAN
  • Link-Pulse Detection for Determining Wire Rate
• Low-Power CMOS Technology - Green PC Compatible
• Magic Packet^TM Remote Wake-Up Scheme
• Microsoft^TM Advanced Power Management
  • PCI Specification Compatible for Low Power/Sleep Mode
  • Advanced Configuration and Power Interface (ACPI)
• IEEE Standard 1149.1 Test-Access Port (JTAG)
• 144-Pin Thin Quad Flat Packages and Quad Flat Packages (PCM and PGE)<

  Ethernet is a registered trademark of Xerox Corporation. Magic Packet is a trademark of Advanced Micro Devices (AMD). Microsoft is a registered trademark of Microsoft Corp. ThunderLAN, Adaptive Performance Optimization, and TI are trademarks of Texas Instruments Incorporated.

description

ThunderLAN is a high-speed networking architecture that provides a complete PCI-to-10 Base-T/AUI Ethernet solution with the flexibility to handle 100-Mbps Ethernet protocols as networking demands grow.

The TNETE100PM, an implementation of the ThunderLAN architecture (see Figure 1), is an intelligent-protocol network interface. The ThunderLAN SRAM FIFO-based architecture eliminates the need for external memory and offers a single-chip glueless PCI-to-10 Base-T/AUI (IEEE 802.3) solution with an on-board physical layer interface. Modular support for 100 Base-T (IEEE 802.3u) and 100VG-AnyLAN (IEEE 802.12) is provided by a superset of the industry-standard media-independent interface (MII). ThunderLAN uses a single driver suite to support multiple networking protocols.

The glueless PCI interface supports 32-bit streaming, operates at speeds up to 33 MHz, and is capable of internal data-transfer rates up to 2 Gbps, taking full advantage of all available PCI bandwidth. The TNETE100PM offers jumperless autoconfiguration using PCI configuration read/write cycles. Customizable configuration registers, which can be autoloaded from an external serial EEPROM, allow designers of TNETE100PM-based systems to give their systems a unique identification code. The TNETE100PM PCI interface, developed in conjunction with other leaders in the semiconductor and computer industries, has been tested vigorously on multiple platforms to ensure compatibility across a wide array of available PCI products. In addition, the ThunderLAN drivers and ThunderLAN architecture use TI's patented Adaptive Performance Optimization (APO) technology to adjust critical parameters for minimum latency dynamically, minimum host CPU utilization, and maximum system performance. This technology ensures that the maximum capabilities of the PCI interface are used by automatically tuning the controller to the specific system in which it is operating.

The MII, an industry-standard interface for connecting a variety of external IEEE 802.3u physical layer interfaces, is supported fully by the TNETE100PM. In addition, the TNETE100PM features an IEEE 802.12-compliant superset of the MII to allow for support of 100VG-AnyLAN physical layer interfaces. This allows TNETE100PM-based systems to support 100 Base-TX, 100 Base-FX, 100 Base-T4, and 100VG-AnyLAN cabling schemes for maximum flexibility as each new physical layer interface becomes available in the marketplace.

An intelligent protocol handler (PH) implements the serial protocols of the network. The PH is designed for minimum overhead related to multiple protocols, using common state machines to implement 95% of the total protocol handler. On transmit, the PH serializes data, adds framing and cyclic redundancy check (CRC) fields, and interfaces to the network physical layer (PHY) chip. On receive, it provides address recognition, CRC and error-checking, frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by way of circular-buffer FIFOs in the FIFO SRAM.

ThunderLAN is the first multimedia-ready architecture and is capable of prioritizing data regardless of the selected protocol. The demand-priority protocol supports two priorities of frames: normal and priority. The two transmit channels provide independent host channels for these two frame types. Carrier-sense multiple access with collision detection (CSMA/CD) protocols only support a single priority of frame, but the two channels can be used to prioritize network access. All received frames pass through the single receive channel.

Compliant with IEEE Standard 1149.1 (JTAG), the TNETE100PM provides a five-pin test-access port that is used for boundary-scan testing.

The TNETE100PM is available in a 144-pin thin quad flat package (TQFP) and quad flat package (QFP).

View more information about generic part numbers:TNETE100PM

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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