SPWS018B - MARCH 1995 - REVISED MAY 1996
ThunderLAN is a high-speed networking architecture that provides a complete PCI-to-10 Base-T/AUI Ethernet solution. The TNETE110, an implementation of the ThunderLAN architecture, is an intelligent network protocol interface. The ThunderLAN SRAM FIFO-based architecture eliminates the need for external memory and offers a single-chip glueless PCI-to-10 Base-T/AUI (IEEE 802.3) solution with an on-board physical layer interface.
The glueless PCI interface supports 32-bit streaming, operates at speeds up to 33 MHz and is capable of internal data transfer rates up to 2 Gbps, taking full advantage of all available PCI bandwidth. The TNETE110 offers jumperless autoconfiguration using PCI configuration read/write cycles. Customizable configuration registers, which can be autoloaded from an external serial EEPROM, allow designers of TNETE110-based systems to give their systems a unique identification code. The TNETE110 PCI interface, developed in conjunction with other leaders in the semiconductor and computer industries, has been tested vigorously on multiple platforms to ensure compatibility across a wide array of available PCI products. In addition, the ThunderLAN drivers and ThunderLAN architecture use TI's patented Adaptive Performance Optimization (APO) technology to adjust critical parameters dynamically for minimum latency, minimum host CPU utilization, and maximum system performance. This technology ensures that the maximum capabilities of the PCI interface are used by automatically tuning the adapter to the specific system in which it is operating.
An intelligent protocol handler (PH) implements the serial protocols of the network. The PH is designed for minimum overhead related to multiple protocols, using common state machines to implement 95% of the total protocol handler. On transmit, the PH serializes data, adds framing and cyclic redundancy check (CRC) fields, and interfaces to the network physical layer (PHY) chip. On receive, it provides address recognition, CRC and error checking, frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by way of circular buffer pointers in the FIFO SRAM.
Compliant with IEEE Standard 1149.1, the TNETE110 provides a 5-pin test-access port that is used for boundary-scan testing.
The TNETE110 is available in a 144-pin quad flat package (PCE suffix).
View more information about generic part numbers:TNETE110
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