SPWS014A - APRIL 1994 - REVISED MARCH 1995
IBM and Token-Ring Network are trademarks of International Business Machines Corporation. PacketBlaster is a trademark of Texas Instruments Incorporated. Ethernet is a trademark of Xerox Corporation.
PAL® is a registered trademark of Advanced Micro Devices, Inc. Other companies also manufacture programmable array logic devices.
The TI380C27 is a single-chip network-communications processor (commprocessor) that supports token-ring or Ethernet local area networks (LANs). Token ring at a data rate of either 16 Mbps or 4 Mbps or Ethernet at a data rate of either 10 Mbps (half duplex) or 20 Mbps (full duplex) can be selected. A flexible configuration scheme allows network type and speed to be configured by hardware or software. This allows the design of LAN subsystems that support both token-ring and Ethernet networks by electrically or physically switched network front-end circuits. In addition, the TI380C27 can be used with the TI380FPA PacketBlaster for maximum performance.
The TI380C27 token-ring capability conforms to ISO 8802-5/IEEE 802.5-1992 standards and has been verified to be completely IBM Token-Ring Network compatible. By integrating the essential control building blocks needed on a LAN-subsystem card into one device, the TI380C27 can ensure that this IBM compatibility is maintained in silicon.
The TI380C27 Ethernet capability conforms to ISO/IEC 8802-3 (ANSI/IEEE Std. 802.3) CSMA/CD standards and the Ethernet Blue Book standard.
The high degree of integration of the TI380C27 makes it a virtual LAN subsystem on a single chip. Protocol handling, host-system interfacing, memory interfacing, and communications processing are all provided through the TI380C27. To complete LAN-subsystem design, only the network-interface hardware, local memory, and minimal additional components such as PAL® devices and crystal oscillators need to be added.
The TI380C27 provides a 32-bit system-memory address reach with a high-speed bus-master DMA interface that supports rapid communications with the host system. In addition, the TI380C27 supports direct I/O and a low-cost 8- or 16-bit pseudo-DMA interface that requires only a chip select to work directly on an 80x8x 8-bit slave I/O interface. Finally, selectable 80x8x or 68xxx-type host-system bus and memory organization add to design flexibility.
The TI380C27 supports addressing for up to 2M bytes of local memory. This expanded memory capacity can improve LAN-subsystem performance by minimizing the frequency of host LAN-subsystem communications by allowing larger blocks of information to be transferred at one time. The support of large local memory is important in applications that require large data transfers (such as graphics or data-base transfers) and in heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed by the host.
The proprietary CPU used in the TI380C27 allows protocol software to be downloaded into RAM or stored in ROM in the local-memory space. By moving protocols to the LAN subsystem, overall system performance is increased. This is accomplished by the offloading of processing from the host system to the TI380C27, which can also reduce LAN-subsystem-to-host communications. As other protocol software is developed, greater differentiation of end products with enhanced system performance will be possible.
In addition, the TI380C27 includes hardware counters that provide real-time error detection and automatic frame-buffer management. These counters control system-bus retries, control burst size, and track host and LAN-subsystem buffer status. Previously, these counters needed to be maintained in software. By integrating them into hardware, software overhead is removed and LAN-subsystem performance is improved.
The TI380C27 implements a TI-patented enhanced-address-copy-option (EACO) interface. This interface supports external address-checking devices, such as the TMS380SRA source-routing accelerator. The TI380C27 has a 128-word external I/O space in its memory to support external address-checker devices and other hardware extensions to the TMS380 architecture.
The major blocks of the TI380C27 include the communications processor (CP), the system interface (SIF), the memory interface (MIF), the protocol handler (PH), the clock generator (CG), and the adapter-support function (ASF), as shown in the functional block diagram.
The TI380C27 is available in a 144-pin plastic thin quad flat package (PGE suffix) and is characterized for operation from 0°C to 70°C.
The TI380C27 has a bus interface to the host system, a bus interface to local memory, and an interface to the physical-layer circuitry. Pin names starting with the letter S attach to the host-system bus and pin names starting with the letter M attach to the local-memory bus. Active-low signals have names with overbars; e.g., SCS\.
View more information about generic part numbers:TI380C27
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.