TI380C25 TOKEN-RING COMMPROCESSOR

SPWS012 - JANUARY 1995

features

• IEEE 802.5 and IBM Token-Ring Network^TM Compatible
• Compatible With TI380FPA FNL PacketBlaster^TM
• Token-Ring Features
  • 16- or 4-Megabit-per-Second Data Rates
  • Supports up to 18K-Byte Frame Size (16-Mbps Operation Only)
  • Supports Universal-and Local-Network Addressing
  • Early Token-Release Option (16-Mbps Operation Only)
  • Compatible With the TMS38054
• Expandable Local LAN-Subsystem Memory Space up to 2 Megabytes
• Glueless Interface to DRAMs
• High-Performance 16-Bit CPU for Communications-Protocol Processing
• 1- to 16.5-Megabyte-per-Second High-Speed Bus Master DMA Interface
• Low-Cost Host-Slave I/O Interface Option
• Up to 32-Bit Host Address Bus
• Selectable Host System-Bus Options
• Adapter Local-Bus Speed Is Switchable Between 4 MHz and 6 MHz
• 80x8x or 68xxx-Type Bus and Memory Organization
  • 8- or 16-Bit Data Bus on 80x8x Buses
  • Optional Parity Checking
• Dual-Port DMA and Direct I/O Transfers to Host Bus
• Supports 8- or 16-Bit Pseudo-DMA Operation
• Enhanced-Address-Copy-Option (EACO) Interface Supports External Address-Checking Logic for Bridging or External Custom Applications
• Support for Module High-Impedance In-Circuit Testing
• Built-In Real-Time Error Detection
• Bring-Up and Self-Test Diagnostics With Loopback
• Automatic Frame-Buffer Management
• 2- to 33-MHz System-Bus Clock
• Slow-Clock Low-Power Mode
• Single 5-V Supply
• 0.8-um CMOS Technology
• 250-mA Typical Latch-Up Immunity at 25°C
• ESD Protection Exceeds 2000 V
• 144-Pin Plastic Thin Quad Flat Package (PGE Suffix)
• Operating Temperature Range 0°C to 70°C

IBM and Token-Ring Network are trademarks of International Business Machines Corp. PacketBlaster is a trademark of Texas Instruments Incorporated.

pin assignments

description

The TI380C25 is a single-chip network-communications processor (commprocessor) that supports token-ring local area networks (LANs) at data rates of 16 Mbps or 4 Mbps. The TI380C25 conforms to ISO 8802-5/IEEE 802.5-1992 standards and has been verified to be completely IBM Token-Ring Network compatible. By integrating the essential control building blocks needed on a LAN-subsystem card into one device, the TI380C25 ensures that this IBM compatibility is maintained in silicon.

The high degree of integration of the TI380C25 makes it a virtual LAN subsystem on a single chip. Protocol handling, host-system interfacing, memory interfacing, and communications processing are all provided through the TI380C25. To complete LAN-subsystem design, only the network-interface hardware, local memory, and minimal additional components such as PAL^® devices and crystal oscillators need to be added.

The TI380C25 provides a 32-bit system-memory address reach with a high-speed bus-master DMA interface that supports rapid communications with the host system. In addition, the TI380C25 supports direct I/O and a low-cost 8- or 16-bit pseudo-DMA interface that requires only a chip select to work directly on an 80x8x 8-bit slave I/O interface. Finally, selectable 80x8x or 68xxx-type host-system bus and memory organization add to design flexibility.

The TI380C25 supports addressing for up to 2M bytes of local memory. This expanded memory capacity can improve LAN-subsystem performance by allowing larger blocks of information to be transferred at one time and minimizing the frequency of host LAN-subsystem communications. The support of large local memory is important in applications that require large data transfers (such as graphics or database transfers) and in heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed by the host.

The proprietary CPU used in the TI380C25 allows protocol software to be downloaded into RAM or stored in ROM in the local-memory space. By moving protocols (such as LLC) to the LAN-subsystem, overall system performance is increased. This is accomplished by offloading the processing from the host system to the TI380C25, which can also reduce LAN-subsystem-to-host communications. As other protocol software is developed, greater differentiation of end products with enhanced system performance is possible.

In addition, the TI380C25 includes hardware counters that provide real-time error detection and automatic frame-buffer management. These counters control system-bus retries and burst size, and track host and LAN-subsystem buffer status. Previously, these counters needed to be maintained in software. Integrating them into hardware removes software overhead and improves LAN-subsystem performance.

The TI380C25 implements a TI-patented enhanced-address-copy-option (EACO) interface. This interface supports external address-checking devices, such as the TMS380SRA source-routing accelerator. The TI380C25 has a 128-word external I/O space in its memory to support external address-checker devices and other hardware extensions to the TMS380 architecture.

The major blocks of the TI380C25 include the communications processor (CP), the system interface (SIF), the memory interface (MIF), the protocol handler (PH), the clock generator (CG), and the adapter-support function (ASF), as shown in the functional block diagram.

The TI380C25 is available in a 144-pin plastic thin quad flat package (PGE suffix) and is characterized for operation from 0°C to 70°C.

The TI380C25 has a bus interface to the host system, a bus interface to local memory, and an interface to the physical-layer circuitry. Pin names starting with the letter S attach to the host-system bus, and pin names starting with the letter M attach to the local-memory bus.

PAL^® is a registered trademark of Advanced Micro Devices, Inc. Other companies also manufacture programmable array logic devices.

View more information about generic part numbers:TI380C25

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