TMS34020, TMS34020AGRAPHICS PROCESSORS

SPVS004D - MARCH 1990 - REVISED NOVEMBER 1993

features

• Instruction Cycle Time
  • 100 ns...TMS34020A-40
  • 125 ns...TMS34020-32
  • 125 ns...TMS34020A-32
• Fully Programmable 32-Bit General-Purpose Processor With 512-Megabyte Linear Address Range (Bit Addressable)
• Second-Generation Graphics Processor
  • Object Code Compatible With the TMS34010
  • Enhanced Instruction Set
  • Optimized Graphics Instructions
  • TMS34082 Graphics Floating-Point Interface
• Pixel Processing, XY Addressing, and Window Checking Built into the Instruction Set
• Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit Pixel Size With 16 Boolean and 6 Arithmetic Pixel-Processing Options (Raster-Ops)
• 512-Byte LRU On-Chip Instruction Cache
• Optimized DRAM/VRAM Interface
  • Page-Mode for Burst Memory Operations up to 40 Megabytes per Second
  • Dynamic Bus Sizing (16-Bit and 32-Bit Transfers)
  • Byte-Oriented CAS\ Strobes
• Flexible Host Processor Interface
  • Supports Host Transfers at up to 20 Megabytes per Second
  • Direct Access to All of the TMS34020 Address Space
  • Implicit Addressing
  • Prefetch for Enhanced Read Access
• Flexible Multiprocessor Interface
• Programmable CRT Control
  • Composite Sync Mode
  • Separate Sync Mode
  • Synchronization to External Sync
• Direct Support for Special Features of 1M VRAMs
  • Load Write Mask
  • Load Color Mask
  • Block Write
  • Write Using the Write Mask

description

The TMS34020 and the TMS34020A graphics processors are the second generation of an advanced high-performance CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in instruction cache, the ability to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics operations, the TMS34020 and TMS34020A provide user-programmable control of the CRT interface as well as the memory interface (both standard DRAM and multiport video RAM). The 4-gigabit (512-megabyte) physical address space is addressable on bit boundaries using variable-width data fields (1 to 32 bits). Additional graphics addressing modes support 1-, 2-, 4-, 8-, 16- and 32-bit wide pixels.

The information contained in this data sheet is applicable to both the TMS34020 and the TMS34020A, except that pertaining to clock stretch, which begins on page 21. Use of the term TMS34020 shall refer to both devices except where noted.

View more information about generic part numbers:TMS34020A

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