TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039 - FEBRUARY 1996

features

• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
• 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
• Compare Select Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
• Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units
• Data Bus With a Bus Holder Feature
• 192K × 16-Bit Maximum Addressable Memory Space (64K Words Program, 64K Words Data, and 64K Words I/O)
• On-Chip ROM with Some Configurable to Program/Data Memory
• Dual-Access On-Chip RAM
• Single-Instruction Repeat and Block Repeat Operations for Program Code
• Block Memory Move Instructions for Better Program and Data Management
• Instructions With a 32-Bit Long Word Operand
• Instructions With Two- or Three-Operand Reads
• Arithmetic Instructions With Parallel Store and Parallel Load
• Conditional Store Instructions
• Fast Return From Interrupt
• On-Chip Peripherals
  • Software-Programmable Wait-State Generator and Programmable Bank Switching
  • On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
  • Full-Duplexed Serial Port to Support 8- or 16-Bit Transfers ('C541, 'LC541, 'VC541, 'LC544, 'VC544, 'LC545, 'VC545, 'LC546, and 'VC546 Only)
  • Time-Division Multiplexed (TDM) Serial Port ('C542, 'LC542, 'VC542, 'LC543 and 'VC543 Only)
  • Buffered Serial Port (BSP) ('C542, 'LC542 'VC542, 'LC543, 'VC543, 'LC545, 'VC545, 'LC546, and 'VC546 Only)
  • 8-Bit Parallel Host Port Interface (HPI) ('C542, 'LC542, 'VC542, 'LC545, and 'VC545 Only)
  • One 16-Bit Timer
  • External-Input/Output (XIO) Off Control to Disable the External Data Bus, Address Bus and Control Signals
• Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
• CLKOUT Off Control to Disable the CLKOUT
• On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1^[dagger] (JTAG) Boundary Scan Logic
• 25-ns Single-Cycle Fixed-Point Instruction Execution Time [40 million instructions per second (MIPS)] for 5-V Power Supply ('C541 and 'C542 Only)
• 20-ns and 25-ns Single-Cycle Fixed-Point Instruction Execution Time (50 MIPS and 40 MIPS) for 3-V Power Supply ('LC54x and 'VC54x)

  ^[dagger] IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

description

The TMS320C54x, TMS320LC54x and TMS320VC54x fixed-point, digital signal processor (DSP) families are fabricated with a combination of an advanced modified Harvard architecture which has one program memory bus and three data memory buses. These processors also provide a central arithmetic logic unit (CALU) which has a high-degree of parallelism and application-specific hardware logic, on-chip memory, additional on-chip peripherals. These DSP families also provide a highly specialized instruction set which is the basis of the operational flexibility and speed of these DSPs.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that all can be performed in a single machine cycle. In addition, the 'C54x, 'LC54x and 'VC54x versions include the control mechanisms to manage interrupts, repeated operations, and function calling.

Table 1 provides an overview of the 'C54x/'LC54x/'VC54x generation of DSPs. The table shows the capacity of on-chip RAM and ROM memories, the peripherals, the execution time of one machine cycle, and the type of package with its total pin count. Use the information in Table 1 to select the best processor for each application.

Legend: TQFP = Thin Quad Flat Pack

^[dagger] The dual-access RAM can be configured as data memory or program and data memory.

^[Dagger] For 'C541/'LC541/'VC541/'LC544/'VC544, 8K words of ROM can be configured as program memory or program/data memory.

^§ TDM and buffered serial ports

^¶ For 'LC545/'VC545/'LC546/'VC546, 16K words of ROM can be configured as program memory or program/data memory.

^# Standard and buffered serial ports

^[dagger] DV_SS and DV_DD are power supplies for I/O pins while CV_SS and CV_DD are power supplies for core CPU.

The pin function table on the following pages lists each pin number, signal, function, and operating mode(s) for the TMS320LC542PBK/'VC542PBK (128-pin) packages.

View more information about generic part numbers:TMS320VC541, TMS320VC541-40, TMS320VC541-50

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.

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