TMS320C40 DIGITAL SIGNAL PROCESSOR

SPRS038 - JANUARY 1996

features

Highest Performance Floating-Point Digital Signal Processor (DSP)
- '320C40-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 384M Bytes/s
- '320C40-50: 40-ns Instruction Cycle Time
- '320C40-40: 50-ns Instruction Cycle Time
Six Communications Ports
Six-Channel Direct Memory Access (DMA) Coprocessor
Single-Cycle Conversion to and From IEEE-754 Floating-Point Format
Single Cycle, 1/x, 1/
Source-Code Compatible With TMS320C3x
Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers
Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers
IEEE 1149.1^{^[dagger]} (JTAG) Boundary Scan Compatible
Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers:
- High Port-Data Rate of 120M Bytes/s ('C40-60) (Each Bus)
- 16G-Byte Continuous Program/Data/Peripheral Address Space
- Memory-Access Request for Fast, Intelligent Bus Arbitration
- Separate Address-Bus, Data-Bus, and Control-Enable Pins
- Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
325-Pin Ceramic Grid Array (GF Suffix)
Fabricated Using 0.72-um Enhanced Performance Implanted CMOS (EPIC^TM) Technology by Texas Instruments (TI^TM)
Software-Communication-Port Reset
NMI\ With Bus-Grant Feature

Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance
On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
- 512-Byte Instruction Cache
- 8K Bytes of Single-Cycle Dual-Access Program or Data RAM
- ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports
IDLE2 Clock-Stop Power-Down Mode
5-V Operation

^{^[dagger]} IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary-Scan Architecture EPIC and TI are trademarks of Texas Instruments Incorporated.

block diagram

functions

This section lists signal descriptions for the '320C40 device. The '320C40 pin functions table lists each signal, number of pins, operating mode(s) (that is, input, output, or high-impedance state as indicated by I, O, or Z, respectively), and function. The signals are grouped according to function.

Pin Functions

^{^[dagger]} I = input, O = output, Z = high impedance

^{^[Dagger]} Signal's effective address range is defined by the local/global STRB ACTIVE bits.

^{^[dagger]} I = input, O = output, Z = high impedance

GF Package Pin Assignments -- Alphabetical Listing

GF Package Pin Assignments -- Numerical Listing

memory map

Figure 1 shows the memory map for the '320C40. Refer to the TMS320C4x User's Guide (literature number SPRU063B) for a detailed description of this memory mapping.

Figure 1. Memory Map for '320C40

description

The '320C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-um, double-level metal CMOS technology. The '320C40 is a part of the fourth generation of DSPs from Texas Instruments and is designed primarily for parallel processing.

Title: DIGITAL SIGNAL PROCESSOR
Product Family: TMS320C4X FLOATING POINT DSP
Device Functionality: 32 BIT FLOATING POINT,5V,PARALLEL PROCESSING
Orderable Devices: TMP320C40TABL50, TMP320C40TABL60, TMS320C40GFL40, TMS320C40GFL50, TMS320C40GFL60, TMS320C40GFL50, TMP320C40TABL60, TMS320C40GFL60

View the complete PDF datasheet: sprs038.pdf (692 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:TMP320C40, TMS320C40, TMS320C40-50, TMS320C40-60

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.