TMP320C40KGD, SMJ320C40KGD FLOATING-POINT DIGITAL SIGNAL PROCESSORS KNOWN GOOD DIE

SPRS036 - NOVEMBER 1995

features

Commercial Operating Temperature Range 0°C to 70°C
Military Operating Temperature Range -55°C to 125°C; QML Processing
Highest Performance Floating-Point Digital Signal Processor (DSP)
- Instruction Cycle Time of 40 ns 275 MOPS 50 MFLOPS 20 MIPS 320 Mbytes/s
Six Communication Ports
Six-Channel Direct Memory Access (DMA) Coprocessor
Support for IEEE, 1/x, 1/
Source-Code Compatible with TMP/SMJ320C30
Validated Ada Compiler
Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers
Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers
IEEE 1149.1^{^[dagger]} (JTAG) Boundary-Scan Compatible
Two External Data and Address Buses Supporting Shared Memory Systems and High-Data Rate, Single-Cycle Transfers:
- High Port-Data Rate of 80 Mbytes/s
- 4G-Word Continuous Program/Data/Peripheral Address Space
- Memory-Access Request for Fast, Intelligent Bus Arbitration
- Separate Address, Data, and Control-Enable Pins
- Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
Fabricated Using 0.8-um Enhanced Performance Implanted CMOS (EPIC^TM) Technology by Texas Instruments (TI^TM)
Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained CPU Performance
On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
- 128-Word Instruction Cache
- 2K-Words of Single-Cycle Dual Access Program or Data RAM
- Boot Loader (ROM-Based) Supporting Program Bootup Via 8-, 16-, or 32-Bit Memories Over Any One of the Communication Ports
  EPIC and TI are trademarks of Texas Instruments Incorporated. ^{^[dagger]} IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary-Scan Architecture.

description

The TMP/SMJ320C40KGD DSP is a 32-bit, floating-point processor manufactured in 0.8-um, double-level metal CMOS technology. It is the fourth generation of DSPs from Texas Instruments, and it is the world's first DSP designed for parallel processing. The on-chip parallel processing capabilities of the 'C40 make the immense floating-point performance required by many applications achievable and cost-effective.

The TMP/SMJ320C40 is the first DSP with on-chip communication ports for processor-to-processor communication using simple communication software with no external hardware. This allows connectivity with no external glue logic. The communication ports remove input/output bottlenecks, and the independent smart-DMA coprocessor is able to handle the CPU input/output burden.

The features of the communication ports are:

Six communication ports for direct interprocessor communication and processor I/O
20M-byte/s bidirectional interface on each communication port for high-speed and low-cost multiprocessor interface
Separate input and output first-in, first-out (FIFO) buffers for processor-to-processor communication and I/O
Automatic arbitration and handshaking for direct processor-to-processor connection

The DMA coprocessor allows concurrent I/O and CPU processing for the highest sustained CPU performance. The key features of the DMA coprocessor:

Link pointers that allow DMA channels to auto-initialize
Parallel CPU operation and DMA transfers
Six DMA channels support communication-port-to-memory data transfers

The TMP/SMJ320C40KGD CPU is configured for high-speed internal parallelism for the highest sustained performance. The key features of the CPU are:

Eight operations/cycle
- 40-/32-bit floating-point/integer multiply
- 40-/32-bit floating-point/integer arithmetic and logic unit (ALU) operation
- Two data accesses
- Two address-register updates
IEEE floating-point conversion
Division and square root support
'C30 assembly language compatibility
Byte and halfword accessibility

A key factor in a parallel-processing implementation is the development tools available. The 'C40 is supported by a host of parallel-processing development tools for developing and simulating code easily and for debugging parallel-processing systems. The code generation tools include:

Optimizing ANSI C compiler with a runtime library that supports use of communication ports and DMA
SPOX by Spectron Microsystems Incorporated which provides parallel processing support as well as DMA and communication port drivers
Assembler and linker with support for mapping program and data to parallel processors.

The simulation tools include:

Parallel DSP system-level simulation by Logic Modeling Corporation (LMC) which includes a hardware verification (HV) model and full functional (FF) model
TI software simulator with high-level language debugger interface for simulating a single processor

The hardware development and verification tools include:

Parallel processor in-circuit emulator and high-level language debugger: XDS510
Parallel processor development system with four TMS320C40s; local and global memory; and communication-port connections

Title: FLOATING-POINT DIGITAL SIGNAL PROCESSORS KNOWN GOOD DIE
Product Family: TMS320C4X FLOATING POINT DSP
Device Functionality: FLOATING-POINT DIGITAL SIGNAL PROCESSORS KNOWN GOOD DIE
Orderable Devices: SMJ320C40KGDS60C

View the complete PDF datasheet: sprs036.pdf (120 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SMJ320C40KGD, TMP320C40KGD

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