TMS320C30 DIGITAL SIGNAL PROCESSOR

SPRS032A – APRIL 1996 – REVISED JUNE 1997

features

High-Performance Floating-Point Digital Signal Processor (DSP)

TMS320C30-50 (5V)

40-ns Instruction Cycle Time

275 MOPS, 50 MFLOPS, 25 MIPS

TMS320C30-40 (5V)
50-ns Instruction Cycle Time
220MOPS, 40 MFLOPS, 20 MIPS

TMS320C30-33 (5V)
60-NS Instruction Cycle Time
183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS

TMS320C30-27 (5V)
74-ns Instruction Cycle Time
148.5 MOPS, 27 MFLOPS, 13.5 MIPS

32-Bit High-Performance CPU

16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations

32-Bit Instruction Word, 24-Bit Addresses

Two 1K x 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks

One 4K x 32-Bit Single-Cycle Dual-Access On-Chip ROM Block

On-Chip Memory-Mapped Peripherals:

Two Serial Ports

Two 32-Bit Timers

One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation

Two 32-Bit External Ports

24- and 13-Bit Addresses

0.7-Ω Enhanced Performance Implanted CMOS (EPIC^TM) Technology

208-Pin Plastic Quad Flat Package (PPM Suffix)

181-Pin Grid Array Ceramic Package (GEL Suffix)

Eight Extended-Precision Registers

Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

Two- and Three-Operated Instructions

Parallel Arithmetic and Logic Unit (ALU) and Multiplier Execution in a Single Cycle

Block-Repeat Capability

Zero-Overhead Loops With Single-Cycle Branches

Conditional Calls and Returns

Interlocked Instructions for Multiprocessing Support

Two Sets of Memory Strobes (STRB\ and MSTRB\) and One I/O Strobe (IOSTRB\)

Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation

EPIC and TI are trademarks of Texas Instruments Incorporated.

description

The TMS320C30 is the newest member of the TMS320C3x generation of DSPs from Texas Instruments (TI^TM). The TMS320C30 is a 32-bit floating-point processor manufactured in 0.7-Ω triple-level-metal CMOS technology.

The TMS320C30’s internal busing and special DSP instruction set have the speed and flexibility to execute up to 50 MFLOPS (million floating-point operations per second). The TMS320C30 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

The TMS320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are results of these features.

General-purpose applications are enhanced greatly by the large address space, multiprocessor interface, internally and externally generated wait states, two external interface ports, two timers, serial ports, and multiple interrupt structure. The TMS320C30 supports a wide variety of system applications from host processor to dedicated coprocessor.

High-level language support is implemented easily through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

Title: DIGITAL SIGNAL PROCESSORS
Product Family: TMS320C3X FLOATING POINT DSP
Device Functionality: DIGITAL SIGNAL PROCESSORS
Orderable Devices: TMS320C30GEL, TMS320C30GEL27, TMS320C30GEL40, TMS320C30GEL50, TMS320C30GEL40, TMS320C30GEL50

View the complete PDF datasheet: sprs032a.pdf (745 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:TMS320C30, TMS320C30-40, TMS320C30-50, TMX320C30, TMX320C30-50

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.