TMS320C44 DIGITAL SIGNAL PROCESSOR

SPRS031B - AUGUST 1994 - REVISED DECEMBER 1995

features

Highest Performance Floating-Point Digital Signal Processor (DSP)
- TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes/s
- TMS320C44-50: 40-ns Instruction Cycle Time
Four Communication Ports
Six-Channel Direct Memory Address (DMA) Coprocessor
Single-Cycle Conversion to and From IEEE-754 Floating-Point Format
Single Cycle, 1/x, 1/x\
Source-Code Compatible With '320C3x and '320C4x
Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers
Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers
IEEE-1149.1^{^[dagger]} (JTAG) Boundary-Scan Compatible
Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers
- High Port-Data Rate of 120M Bytes/s (TMS320C44-60) (Each Bus)
- 128M-Byte Program/Data/Peripheral Address Space
- Memory-Access Request for Fast, Intelligent Bus Arbitration
- Separate Address-Bus, Data-Bus, and Control-Enable Pins
- Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
304-Pin Plastic Quad Flatpack (PDB Suffix)
Fabricated Using 0.72-um Enhanced Performance Implanted CMOS (EPIC^TM) Technology by Texas Instruments (TI^TM)
Separate Internal Program-, Data-, and DMA-Coprocessor Buses for Support of Massive Concurrent I/O of Program and Data, Thereby Maximizing Sustained CPU Performance

IDLE2 Clock-Stop Power-Down Mode
Communication-Port-Direction Pin
On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
- 512-Byte Instruction Cache
- 8K Bytes of Single-Cycle Dual-Access Program or Data RAM
- ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports
Software-Communication-Port Reset
NMI\ With Bus-Grant Feature
^{^[dagger]} IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary-Scan Architecture EPIC and TI are trademarks of Texas Instruments Incorporated.

block diagram

^{^[dagger]} Communication ports 0 and 3 are not connected.

functions

This section lists signal descriptions for the '320C44 device: each signal, number of pins, operating mode(s) (that is, input, output, or high-impedance state as indicated by I, O, or Z, respectively), and function. The signals are grouped according to function.

Pin Functions

^{^[dagger]} I = input, O = output, Z = high impedance

^{^[Dagger]} The effective address range is defined by the local/global STRB\ ACTIVE bits in the memory interface-control registers.

^{^[dagger]} I = input, O = output, Z = high impedance

PDB Package Pin Assignments -- Alphabetical Listing

PDB Package Pin Assignments -- Numerical Listing

memory map

Figure 1 shows the memory map for the '320C44. Refer to the TMS320C4x User's Guide (literature number SPRU063B) for a detailed description of this memory mapping.

Figure 1. Memory Map for the '320C44

description

The TMS320C44 DSP is a 32-bit, floating-point processor manufactured in 0.72-um double-level-metal CMOS technology. The TMS320C44 is part of the TMS320C4x generation of DSPs from Texas Instruments. The on-chip parallel-processing capabilities of the 'C44 make the immense floating-point performance required by many applications achievable.

Title: DIGITAL SIGNAL PROCESSOR
Product Family: TMS320C4X FLOATING POINT DSP
Device Functionality: DIGITAL SIGNAL PROCESSOR
Orderable Devices: TMS320C44GFW50, TMS320C44GFW60, TMS320C44GFWA, TMS320C44PDB50, TMS320C44PDB60, TMS320C44PDB50, TMS320C44PDB60

View the complete PDF datasheet: sprs031b.pdf (589 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:TMS320C44, TMS320C44-50, TMS320C44-60, TMX320C44

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.