SOCS022B - NOVEMBER 1990
The TMS3473B is a monolithic CMOS integrated circuit designed to drive the parallel image-area gate (IAG), parallel storage-area gate (SAG), and antiblooming gate (ABG) inputs of the Texas Instruments virtual-phase CCD image sensors. The TMS3473B interfaces the CCD image sensor to a user-defined timing generator; it receives TTL input signals from the timing generator and outputs level-shifted and slew-rate-adjusted signals to the image sensor.
The TMS3473B allows operation of the CCD image sensor in either the interlace or noninterlace mode. When the TMS3473B I\/N input is connected to VSS, the interlace mode is selected (see Figure 1); when I\/N is connected to VCC, the noninterlace mode is selected (see Figure 2).
The ABOUT output follows the ABIN input and switches between VABG+ and VABG-. The IAOUT and SAOUT outputs follow the IAIN and SAIN inputs, respectively, and switch between VCC and VSS. Additionally, ABOUT and IAOUT can each be made to output midlevel voltages. DC inputs to ABLVL and IALVL determine the mid-level voltages that can be output on ABOUT and IAOUT, respectively. A high logic level on the MIDSEL input causes ABOUT to output its midlevel voltage; a low logic level on MIDSEL causes IAOUT to output its midlevel voltage if the interlace mode is selected.
Slew-rate adjustment of the IAOUT and ABOUT outputs is accomplished by connecting IASR to VCC and ABSR to VABG+ through external resistors. The larger the resistor values used, the longer the rise and fall times will be.
A low logic level on the PD\ input causes the TMS3473B to power down and all outputs to assume their low levels (IAOUT and SAOUT to VSS, ABOUT to VABG-).
The TMS3473B is supplied in the DW package and is characterized for operation from -20°C to 45°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
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