TMS626812B 1 048 576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES

SMOS693A - ocTober 1997 - REVISED APRIL 1998

features

• Organization 1048576 by 8 Bits by 2 Banks
• 3.3-V Power Supply (±10% Tolerance)
• Two Banks for On-Chip Interleaving (Gapless Accesses)
• High Bandwidth - Up to 125-MHz Data Rates
• CAS Latency (CL) Programmable to 2 or 3 Cycles From Column-Address Entry
• Burst Sequence Programmable to Serial or Interleave
• Burst Length Programmable to 1, 2, 4, or 8
• Chip Select and Clock Enable for Enhanced System Interfacing
• Cycle-by-Cycle DQ Bus Mask Capability
• Auto-Refresh and Self-Refresh Capabilities
• 4K Refresh (Total for Both Banks)
• High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface
• Power-Down Mode
• Compatible With JEDEC Standards
• Pipeline Architecture
• Temperature Ranges Operating, 0°C to 70°C Storage, - 55°C to 150°C
• Intel PC100 Compliant (-8A, -8, and -10 Devices)
• Performance Ranges:

^† CL = CAS latency

description

The TMS626812B is a high-speed, 16777216-bit synchronous dynamic random-access memory (SDRAM) device organized as follows:

• Two banks of 1048576 words with 8 bits per word (TMS626812B)

All inputs and outputs of the TMS626812B series are compatible with the LVTTL interface.

The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance the use with high-speed microprocessors and caches.

The TMS626812B SDRAM is available in a 400-mil, 44-pin surface-mount thin small-outine package (TSOP) (DGE suffix).

View more information about generic part numbers:TMS626412B, TMS626812B

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.

(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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