TMS626162A 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMOS692B - JULY 1997 - REVISED MARCH 1998

features

• Organization 512K × 16 Bits × 2 Banks
• 3.3-V Power Supply (±10% Tolerance)
• Two Banks for On-Chip Interleaving (Gapless Accesses)
• High Bandwidth - Up to 100-MHz Data Rates
• CAS Latency (CL) Programmable to Two or Three Cycles From Column-Address Entry
• Burst Sequence Programmable to Serial or Interleave
• Burst Length Programmable to 1, 2, 4, 8, or Full Page
• Chip Select and Clock Enable for Enhanced-System Interfacing
• Cycle-by-Cycle DQ-Bus Mask Capability With Upper- and Lower-Byte Control
• Auto-Refresh and Self-Refresh Capability
• 4K Refresh (Total for Both Banks)
• High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface
• Power-Down Mode
• Compatible With JEDEC Standards
• Pipeline Architecture
• Temperature Ranges: Operating, 0°C to 70°C Storage, - 55°C to 150°C

  	SYNCHRONOUS CLOCK CYLE TIME		ACCESS TIME CLOCK TO OUTPUT		REFRESH INTERVAL
  	tCK3 (CL† = 3)	tCK2 (CL = 2)	tAC3 (CL = 3)	tAC2 (CL = 2)	tREF
  '626162A-10	10 ns	15 ns	7 ns	7 ns	64 ms

  ^† CL = CAS latency

description

The TMS626162A is a high-speed 16777216-bit synchronous dynamic random-access memory (SDRAM) device organized as two banks of 524288 words with 16 bits per word.

All inputs and outputs of the TMS626162A series are compatible with the LVTTL interface.

The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed microprocessors and caches.

The TMS626162A SDRAM is available in a 400-mil, 50-pin surface-mount TSOP package (DGE suffix).

View more information about generic part numbers:TMS626162A

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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