TMS626812A 1 048 576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMOS691B - JULY 1997 - REVISED APRIL 1998

features

• Organization 1M Words × 8 Bits × 2 Banks
• 3.3-V Power Supply (±10% Tolerance)
• Two Banks for On-Chip Interleaving (Gapless Accesses)
• High Bandwidth - Up to 100-MHz Data Rates
• CAS Latency (CL) Programmable to 2 or 3 Cycles From Column-Address Entry
• Burst Sequence Programmable to Serial or Interleave
• Burst Length Programmable to 1, 2, 4, or 8
• Chip Select and Clock Enable for Enhanced-System Interfacing
• Cycle-by-Cycle DQ-Bus Mask Capability
• Auto-Refresh and Self-Refresh Capabilities
• 4K Refresh (Total for Both Banks)
• High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface
• Power-Down Mode
• Compatible With JEDEC Standards
• Pipeline Architecture
• Temperature Ranges Operating, 0°C to 70°C Storage, - 55°C to 150°C
• Performance Ranges:

  	SYNCHRONOUS CLOCK CYCLE TIME		ACCESS TIME (CLOCK TO OUTPUT)		REFRESH TIME INTERVAL
  	tCK3 (CL†=3)	tCK2 (CL=2)	tAC3 (CL=3)	tAC2 (CL=2)
  '626812A-10	10 ns	15 ns	7 ns	7 ns	64 ms

  ^† CL = CAS latency

description

The TMS626812A is a high-speed, 16777216-bit synchronous dynamic random-access memory (SDRAM) device organized as:

• Two banks of 1048576 words with 8 bits per word

All inputs and outputs of the TMS626812A series are compatible with the LVTTL interface.

The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance the use with high-speed microprocessors and caches.

The TMS626812A SDRAM is available in a 400-mil, 44-pin surface-mount TSOP package (DGE suffix).

View more information about generic part numbers:TMS626412A, TMS626812A

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.

(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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