TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997

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features

Organization... 512K × 16 × 2 Banks
3.3-V Power Supply (±10% Tolerance)
Two Banks for On-Chip Interleaving (Gapless Accesses)
High Bandwidth - Up to 83-MHz Data Rates
CAS Latency (CL) Programmable to 2 or 3 Cycles From Column-Address Entry
Burst Sequence Programmable to Serial or Interleave
Burst Length Programmable to 1, 2, 4, 8, or Full Page
Chip Select and Clock Enable for Enhanced-System Interfacing
Cycle-by-Cycle DQ-Bus Mask Capability With Upper and Lower Byte Control
Auto-Refresh and Self-Refresh Capability
4K Refresh (Total for Both Banks)
High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface
Power-Down Mode
Compatible With JEDEC Standards
Pipeline Architecture
Temperature Ranges: Operating, 0°C to 70°C Storage, - 55°C to 150°C
-12A speed device is supported only at -5/+10% V_CC
CL = CAS latency

description

The TMS626162 device is a high-speed 16777216-bit synchronous dynamic random- access memory (SDRAM) organized as two banks of 524288 words with 16 bits per word.

All inputs and outputs of the TMS626162 series are compatible with the LVTTL interface.

The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed microprocessors and caches.

The TMS626162 SDRAM is available in a 400-mil, 50-pin surface-mount TSOP package (DGE suffix).

Title: 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
Product Family: SDRAM
Device Functionality: 16M(1MX16), PIPELINE, 2 BANKS
Orderable Devices: TMS626162-12DGE, TMS626162-15DGE

View the complete PDF datasheet: smos683e.pdf (711 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:TMS626162

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