TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES

SMMS694 - AUGUST 1997

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features

Organization
- TM16ER72HP-xx...16777216 × 72 Bits
- TM16ER72LP-xx...16777216 × 72 Bits
Single 3.3-V Power Supply (±10% Tolerance)
JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) With Buffer for Use With Socket
TM16ER72xP-xx -- Uses 18 64M-Bit High-Speed (16M×4-Bit) Dynamic RAMs
High-Speed, Low-Noise LVTTL Interface
High-Reliability 32-Lead 400-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGE Suffix)
Intended for Workstation/Server Applications
Long Refresh Periods:
- TM16ER72HP: 64 ms (4096 Cycles)
- TM16ER72LP: 64 ms (8192 Cycles)
3-State Output
Extended-Data-Out (EDO) Operation With CAS\-Before-RAS\ (CBR), RAS\-Only, and Hidden Refresh
Ambient Temperature Range 0°C to 70°C
Gold-Plated Contacts
Performance Ranges ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE t_RAC t_CAC t_AA t_HPC (MAX) (MAX) (MAX) (MIN)'16ER72xx-40 40 ns 11 ns 20 ns 16 ns'16ER72xx-50 50 ns 13 ns 25 ns 20 ns'16ER72xx-60 60 ns 15 ns 30 ns 25 ns

description

The TM16ER72HP is a 128M-byte, 168-pin, buffered dual-in-line memory module (DIMM). The DIMM is composed of eighteen TMS465409, 16777216 × 4-bit 4K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 32-pin plastic thin small-outline package (TSOP) (DGE suffix), and two SN74LVC162244 16-bit buffers, each in a 48-lead plastic TSOP package mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895).

The TM16ER72LP is a 128M-byte, 168-pin, buffered DIMM. The DIMM is composed of eighteen TMS464409, 16777216 × 4-bit 8K-refresh EDO DRAMs, each in a 400-mil, 32-pin plastic TSOP (DGE suffix), and two SN74LVC162244 16-bit buffers, each in a 48-lead plastic TSOP package mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895).

These modules are intended for multimodule workstation/server applications where buffering is needed for address and control signals. Two copies of address 0 (A0 and B0) are defined to allow maximum performance for 4-byte applications that interleave between two 4-byte banks. A0 is common to the DRAMs used for DQ0-DQ31, while B0 is common to the DRAMs used for DQ32-DQ63.

Title: 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
Product Family: DIMM
Device Functionality: 128M, BUFFERED, (18) 16MX4 8K-EDO (TSOP)

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