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SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
features
- Organization:
- TM8SK64JPU . . . 8 388 608 x 64 Bits
- Single 3.3-V Power Supply (±10% Tolerance)
- Designed for 66-MHz 4-Clock Systems
- JEDEC 144-Pin Small Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket
- Uses Eight 64M-Bit Synchronous Dynamic RAMs (SDRAMs) (8M × 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs)
- Byte-Read/Write Capability
- Performance Ranges:
- High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface
- Read Latencies 2 and 3 Supported
- Support Burst-Interleave and Burst-Interrupt Operations
- Burst Length Programmable to 1,2,4,and8
- Four Banks for On-Chip Interleaving (Gapless Access)
- Ambient Temperature Range 0°C to 70°C
- Gold-Plated Contacts
- Pipeline Architecture
- Serial Presence Detect (SPD) Using EEPROM
| | SYNCHRONOUS CLOCK CYCLE TIME | ACCESS TIME CLOCK TO OUTPUT | REFRESH INTERVAL |
|---|
| | tCK3 | tCK2 | tAC3 | tAC2 | tREF |
| '8SK64JPU-10 | 10 ns | 15 ns | 8 ns | 9 ns | 64 ms |
| | | | | | |
description
The TM8SK64JPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS664814DGE, 8388608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS690).
Title: 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE-SODIMM
Product Family: SODIMM
Device Functionality: 64M, UNBUFFERED, (8) 8MX8 4K-SDRAM (TSOP)
View the complete PDF datasheet: smms690b.pdf (194 K Bytes) (Requires Acrobat Reader 3.x)View more information about generic part numbers:TM8SK64JPU
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.




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