TM4EP72BPB, TM4EP72BJB, 4194304 BY 72-BIT TM4EP72CPB, TM4EP72CJB 4194304 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES

SMMS686A - AUGUST 1997 - REVISED FEBRUARY 1998

features

• Organization...4194304 × 72 Bits
• Single 3.3-V Power Supply (±10% Tolerance)
• JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) With Buffer for Use With Socket
• TM4EP72xxB-xx -- Uses Eighteen 16M-Bit High-Speed (4M×4-Bit) Dynamic Random Access Memories (DRAMs)
• High-Speed, Low-Noise LVTTL Interface
• High-Reliability Plastic 26-Lead 300-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DJ Suffix) and 26-Lead 300-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGA Suffix)
• Intended for Workstation/Server Applications
• Long Refresh Periods:
  • TM4EP72CxB: 64 ms (4096 Cycles)
  • TM4EP72BxB: 32 ms (2048 Cycles)
• 3-State Output
• Extended-Data-Out (EDO) Operation With CAS\-Before-RAS\ (CBR), RAS\-Only, and Hidden Refresh
• Ambient Temperature Range 0°C to 70°C
• Gold-Plated Contacts
• Performance Ranges ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE t_RAC t_CAC t_AA t_HPC (MAX) (MAX) (MAX) (MIN)'4EP72xxB-50 50 ns 13 ns 25 ns 20 ns'4EP72xxB-60 60 ns 15 ns 30 ns 25 ns'4EP72xxB-70 70 ns 18 ns 35 ns 30 ns

description

The TM4EP72BxB is a 32M-byte, 168-pin, buffered, dual-in-line memory module (DIMM). The DIMM is composed of eighteen TMS427409A, 4194304 × 4-bit 2K refresh EDO DRAMs, each in a 300-mil, 26-lead plastic TSOP (DGA suffix) or SOJ package (DJ suffix), and two SN74LVT162244 16-bit buffers, each in a 48-lead plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS427409A data sheet (literature number SMKS893).

The TM4EP72CxB is a 32M-byte, 168-pin, buffered DIMM. The DIMM is composed of eighteen TMS426409A, 4194304 × 4-bit 4K refresh EDO DRAMs, each in a 300-mil, 26-lead plastic TSOP (DGA suffix) or SOJ package (DJ suffix), and two 16-bit buffers mounted on a substrate with decoupling capacitors. See the TMS427409A data sheet (literature number SMKS893).

These modules are intended for multimodule workstation/server applications where buffering is needed for address and control signals. Two copies of address 0 (A0 and B0) are defined to allow maximum performance for 4-byte applications which interleave between two 4-byte banks. A0 is common to the DRAMs used for DQ0-DQ31, while B0 is common to the DRAMs used for DQ32-DQ63.

View more information about generic part numbers:TM4EP72BJB, TM4EP72BPB, TM4EP72CJB, TM4EP72CPB

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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