TMS29F002T, TMS29F002B 262144 BY 8-BIT FLASH MEMORIES

SMJS848 - AUGUST 1997

features

• Single Power Supply Supports 5-V ±10% Read/Write Operation
• Organization:...
• Array-Blocking Architecture
  • One 16K-Byte Protected-Boot Sector
  • Two 8K-Byte Parameter-Sectors
  • One 32K-Byte Sector
  • 64K-Byte Sectors
  • Any Combination of Sectors Can Be Erased. Supports Full-Chip Erase
  • Any Combination of Sectors Can Be Marked as Read-Only
• Boot-Code Sector Architecture
  • T = Top Sector
  • B = Bottom Sector
• Sector Protection
  • Hardware Protection Method That Disables Any Combination of Sectors From Write or Erase Operations Using Standard Programming Equipment
• Embedded Program/Erase Algorithms
  • Automatically Pre-Programs and Erases Any Sector
  • Automatically Programs and Verifies the Program Data at Specified Address
• JEDEC Standards
  • Compatible With JEDEC Byte Pinouts
  • Compatible With JEDEC EEPROM Command Set
• Fully Automated On-Chip Erase and Program Operations
• 100 000 Program/Erase Cycles
• Low Power Dissipation
• Low Current Consumption
  • Typical Active Read
  • 60-mA Typical Program/Erase Current
  • Less Than 100-uA Standby Current
• All Inputs/Outputs TTL-Compatible
• Erase Suspend/Resume
  • Supports Reading Data From, or Programming Data to, a Sector Not Being Erased
• 40-Pin Thin Small Outline Package (TSOP) (DCD Suffix)
• Detection Of Program/Erase Operation
  • Data Polling and Toggle Bit Feature of Program/Erase Cycle Completion
• High-Speed Data Access at 5-V V_CC±10%
  • 70 Commercial...0°C to 70°C
  • 80 Extended...-40°C to 85°C

description

The is a , single-supply, programmable read-only memory device that can be electrically erased and reprogrammed. This device is organized as , divided into sectors:

• One 16K-byte protected-boot sector
• Two 8K-byte sectors
• One 32K-byte sector
• Three 64K-byte sectors

Any combination of sectors can be marked as read-only or erased. Full chip erasure is also supported.

Sector data protection is afforded by methods that can disable any combination of sectors from write or read operations using standard programming equipment. An on-chip state machine provides an on-board algorithm that automatically pre-programs and erases any sector before it automatically programs and verifies program data at any specified address. The command set is compatible with that of the Joint Electronic Device Engineering Council (JEDEC) standards and is compatible with the JEDEC 2M-byte electrically erasable programmable read-only memory (EEPROM) command set. A suspend/resume feature allows access to

unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible. Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector that is not being erased.

Device operations are selected by writing JEDEC-standard commands into the command register using standard microprocessor write timings. The command register acts as an input to an internal-state machine which interprets the commands, controls the erase and programming operations, outputs the status of the device, outputs data stored in the device, and outputs the device algorithm-selection code. On initial power up, the device defaults to the read mode.

The device has low power dissipation with a 40-mA active read for the byte mode, 60-mA typical program/erase current mode, and less than 100-uA standby current. These devices are offered with 70 and 80 ns access times. Table 1 and Table 2 show the sector-address ranges. The is offered in a 40-pin (DCD suffix) thin small-outline package.

View more information about generic part numbers:TMS29F002B, TMS29F002T

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