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Data Sheet Abstract

TMS4C2973 245760 BY 12-BIT FIELD MEMORY

SMGS672 - OCTOBER 1997


Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

description

The TMS4C2973 is a field memory (FMEM) that is upwardly and pin-to-pin compatible with the TMS4C2970 and TMS4C2971, except for the consequences of the block size change (40 instead of 80 words per block) on old data access mode enabling (see the section titled ``old-/new-data access").

The device is a two-port memory; data is written in through a 12-bit-wide write port and is read out through a 12-bit-wide read port. Both ports may be operated simultaneously and/or asynchronously. Dynamic storage cells are employed for main data memory to achieve high storage density, but the TMS4C2973 refreshes its cells automatically so that device operation appears fully static to the user. All internal pointers and registers are fully static so that read and write operations can be interrupted for indefinite periods of time without loss of data.

Maximum storage capacity is 245760 words by 12 bits. Addressing is governed by write-address and read-address pointers, which can be easily controlled by the user. The TMS4C2973 can be addressed in a strictly sequential or FIFO manner, but it also offers an optional random-block access mode, which allows the user to direct either pointer to the beginning of any of the 6144 blocks that comprise the address space of the memory.

In sequential addressing mode, the TMS4C2973 functions like a FIFO register. The timing between write-reset and read-reset operations determines the delay or length of the FIFO. Data may be read out as many times as desired after it has been written into the storage array of the memory. Minimum delay between writing and reading is 160 write cycles; maximum delay is one full field plus one block or 245800 words.

If the memory is used as a delay element only, there is no need to reset the read and write address pointers, because they wrap around after passing their maximum value. For details, see the section on wrap-around of pointers.

The TMS4C2973 employs state-of-the-art 16M-bit complementary metal-oxide semiconductor (CMOS) dynamic random-access memory (DRAM) technology for high performance, reliability, and low-power dissipation. The device is rated for operation in the 0°C to 70°C range and is available in a high-reliability 36-lead surface-mount shrink small-outline package (SSOP) (DT suffix).


Title: 245760 BY 12-BIT
Product Family: FMEM
Device Functionality: 3.3V FRAME MEMORY

View the complete PDF datasheet: smgs672.pdf (325 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:TMS4C2973

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