SN75LVDS82 FLATLINK^TM RECEIVER

SLLS259C - NOVEMBER 1996 - REVISED MAY 1998

features

• 4:28 Data Channel Expansion at up to 227.5 Million Bytes per Second (Mbytes/s) Throughput
• Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
• 4 Data Channels and Clock Low-Voltage Differential Channels In and 28 Data and Clock Low-Voltage TTL Channels Out
• Operates from a Single 3.3-V Supply with 250 mW Typ
• 5-V Tolerant SHTDN\ Input
• Falling Clock-Edge-Triggered Outputs
• Packaged in Thin Shrink Small-Outline Package with 20-Mil Terminal Pitch
• Consumes Less Than 1 mW When Disabled
• Wide Phase-Lock Input Frequency Range...31 MHz to 68 MHz
• No External Components Required for PLL
• Inputs Meet or Exceed the Requirements of the ANSI EIA/TIA-644 Standard
• Improved Replacement for the National DS90C582

  FlatLink is a registered trademark of Texas Instruments Incorporated.

description

The SN75LVDS82 FlatLink^TM receiver contains four serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single

integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, over five balanced-pair conductors and expansion to 28 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 or SN75LVDS85 for 21-bit transfers.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×) the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).

The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear (SHTDN\) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low-level on SHTDN\ clears all internal registers to a low level.

The SN75LVDS82 is characterized for operation over ambient air temperatures of 0°C to 70°C.

View more information about generic part numbers:SN75LVDS82

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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