SN75LVDS81 FLATLINK^TM TRANSMITTER

SLLS258A - NOVEMBER1996 - REVISED JANUARY 1997

features

• 28:4 Data Channel Compression at up to 227.5 Million Bytes per Second Throughput
• Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
• 28 Data Channels and Clock In Low-Voltage TTL
• 4 Data Channels and Clock-Out Low-Voltage Differential
• Operates from a Single 3.3-V Supply with 250 mW (Typ)
• 5-V Tolerant Data Inputs
• Falling Clock-Edge-Triggered Inputs
• Packaged in Thin Shrink Small-Outline Package with 20-Mil Terminal Pitch
• Consumes Less Than 1 mW when Disabled
• Wide Phase-Lock Input Frequency Range . . . 31 MHz to 68 MHz
• No External Components Required for PLL
• Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
• Improved Replacement for the National DS90C581

  FlatLink is a registered trademark of Texas Instruments Incorporated.

description

The SN75LVDS81 FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and five low-voltage differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS81 can also be used in 21-bit links with the SN75LVDS86 receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the falling edge of the input clock signal (CLKIN) The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS81 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear (SHTDN\) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on SHTDN\ clears all internal registers to a low level.

The SN75LVDS81 is characterized for operation over free-air temperature ranges of 0°C to 70°C.

View more information about generic part numbers:SN75LVDS81

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