SLLS232A - MARCH 1996 - REVISED MAY 1997
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.
FireWire is a trademark of Apple Computer, Incorporated.
The TSB11LV01 provides the analog transceiver functions needed to implement a single port node in a cable based IEEE 1394-1995 network. The cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB11LV01 is designed to interface with a link layer controller, such as the TSB12C01A.
The TSB11LV01 requires an external 24.576-MHz crystal, which drives an internal phase-locked loop (PLL) generating the required 98.304-MHz reference signal. The 98.304-MHz reference signal is internally divided to provide the 49.152-MHz ±100 ppm system clock signals that control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated link for synchronization of the two chips and is used for resynchronization of the received data. The power-down function, when enabled by asserting the PWRDN terminal high, stops operation of the PLL.
Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the TSB11LV01 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304-Mbits/s as the outbound data-strobe information stream. During transmit, the encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information is transmitted differentially on the TPA cable pair.
NOTE
In this document, phy is the physical layer and link is the link layer controller.
During packet reception the TPA and TPB transmitters of the cable port are disabled, and the receivers of the port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two parallel streams, resynchronized to the local system clock and sent to the associated link.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. In addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. The presence or absence of this bias voltage is an indication of cable connection status. The cable connection status signal is internally debounced in the TSB11LV01. The debounced cable connection status signal initiates a bus reset. On a cable disconnect-to-connect, the debounce delay is 335 ms. On a connect-to-disconnect there is minimal debounce.
The TSB11LV01 provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. The value of this bias voltage has been chosen to allow interoperation between transceiver chips operating from either 5-V nominal supplies or 3-V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of at least 1 uF.
The transmitter circuitry is disabled under the following conditions: powerdown, cable not active, reset, or transmitter disable. The receiver circuitry is disabled during powerdown, cable not active, or receiver disable. The twisted-pair bias voltage circuitry is disabled during the powerdown or reset conditions. The power-down condition occurs when the PWRDN input is asserted high. The cable-not-active condition occurs
when the cable connection status indicates no cable is connected and is not debounced. The device reset condition occurs when the RESET\ input terminal is asserted low. The transmitter disable and receiver disable conditions are determined from the internal logic.
The line drivers in the TSB11LV01 operate in the high-impedance current mode and are designed to work with external 112- line matching resistor networks. One network is provided at each end of each twisted-pair cable. Each network is composed of a pair of series-connected 56- resistors. The midpoint of the pair of resistors that are directly connected to the twisted-pair A-package terminals is connected to the TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B-package terminals is coupled to ground through a parallel resistance-capacitance (R-C) network with the recommended value of 5 k and 250 pF. The values of the external resistors are designed to meet the IEEE 1394-1995 standard specifications when connected in parallel with the internal receiver circuits (see Figure 3).
An internal reference circuit (bandgap) provides stable bias voltages for the TSB11LV01 transceiver circuits. The driver output current, along with other internal operating currents, is set by an external resistor. This resistor is connected between terminals R1 and R0, and has a value of 6 k ±0.5%.
Two of the package terminals set up various test conditions used in manufacturing. These terminals, TESTM1 and TESTM2, should be connected to VCC for normal operation.
Four package terminals are inputs to set four configuration status bits in the self-identification (Self-ID) packet. These terminals are hardwired high or low as a function of the equipment design. PC0, PC1, and PC2 (corresponds to bits 21, 22, and 23 of the Self-ID packet) are three terminals that indicate either the need for power from the cable or the ability to supply power to the cable. The fourth terminal, C/LKON (corresponds to bit 20 of the Self-ID packet), indicates if a node is a contender for bus manager. C/LKON may also output a 6.114-MHz ±100 ppm signal, indicating reception of a link-on packet. See Table 4-29 of the IEEE 1394-1995 standard for additional details.
In order to operate with power supplies as low as 2.7 V, this device is restricted to applications that do not provide cable power. See Note A in clause 4.2.2.2 of the IEEE 1394-1995 standard.
When the TSB11LV01 is used in applications with a 5-V link layer controller, such as the TSB12C01A, the BIAS-5V terminal should be connected to the link layer controller 5-V supply. Otherwise, connect this terminal to DVCC.
A power-down terminal (PWRDN) is provided to allow most of the TSB11LV01 circuits to be powered down to conserve energy in battery-driven applications. A cable status terminal (CNA) provides a high output when the twisted-pair cable port is disconnected. This output is not debounced. The CNA output can determine when to power the device down. In the power-down mode all circuitry is disabled except the CNA detection circuitry.
If the power supply of the TSB11LV01 is removed while the twisted-pair cables are connected, the TSB11LV01 transmitter and receiver circuitry has been designed to present a high-impedance signal to the cable and not load the TPBIAS voltage on the other end of the cable.
View more information about generic part numbers:TSB11LV01
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.