TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS172B - MAY 1994 - REVISED MARCH 1996

features

• Integrated Asynchronous Communications Element Compatible With PCMCIA PC Card Standard Release 2.01
• Consists of a Single TL16C550 ACE Plus PCMCIA Interface Logic
• Provides Common I Bus/Z Bus Microcontroller Inputs for Most Intel^TM and Zilog^TM Subsystems
• Fully Programmable 256-Byte Card Information Structure and 8-Byte Card Configuration Register
• Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop and Parity) to or From Serial Data Stream
• Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
• Selectable Serial Bypass Mode Provides Subsystem With Direct Parallel Access to the FIFOs
• Fully Programmable Serial Interface Characteristics:
• 5-, 6-, 7-, or 8-Bit Characters
• - Even-, Odd-, or No-Parity Bit Generation and Detection
• - 1-, 1 1/2-, or 2-Stop Bit Generation
• - Baud Rate Generation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions
• Provides TL16C450 Mode at Reset Plus Selectable Normal TL16C550 Operation or Extended 64-Byte FIFO Mode
• Selectable Auto-RTS\ Mode Deactivates RTS\ at 14 Bytes in 550 Mode and at 56 Bytes in Extended 550 Mode
• Selectable Auto-CTS\ Mode Deactivates Serial Transfers When CTS\ is Inactive

  Patent Pending. Intel is a trademark of Intel Corporation. Zilog is a trademark of Zilog Corporation.

description

The TL16PC564A is designed to provide all the functions necessary for a Personal Computer Memory Card International Association (PCMCIA) universal asynchronous receiver transmitter (UART) subsystem interface. This interface provides a serial-to-parallel conversion for data to and from a modem coder decoder/digital signal processor (CODEC/DSP) function to a PCMCIA parallel data port format. A computer central processing unit (CPU), through a PCMCIA host controller, can read the status of the asynchronous communications element (ACE) interface at any point in the operation. Reported status information includes the type of transfer operation in process, the status of the operation, and any error conditions encountered.

Attribute memory consists of a 256-byte card information structure (CIS) and eight 8-byte card configuration registers (CCR). The CIS, implemented with a dual port random access memory (DPRAM), is available to both the host CPU and subsystem (modem), as are the CCRs. This DPRAM is used in place of the electrically erasable programmable read-only memory (EEPROM) normally used for the CIS. At power up, attribute memory is initialized by the subsystem.

The TL16PC564A uses a TL16C550 ACE-type core with an expanded 64 × 11 receiver first-in-first-out (FIFO) memory and a 64 × 8 transmitter FIFO memory. The receiver trigger logic flags have been adjusted in order to take full advantage of the increased capacity when in the extended mode. In addition, eight of the UART registers have been mapped into the subsystem (modem) memory space as read-only registers. This allows the subsystem to read UART status information.

A subsystem selectable serial bypass mode has been implemented to allow the subsystem to bypass the serial portion of the UART and write directly to the receiver FIFO and read directly from the transmitter FIFO. The interrupt operation is not affected in this mode.

The TL16PC564A is packaged in a 100-pin thin quad flat package (PZ).

View more information about generic part numbers:TL16PC564A

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