TL16C550B, TL16C550BI ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B - JANUARY 1994 - REVISED AUGUST 1996

features

• Capable of Running With All Existing TL16C450 Software
• After Reset, All Registers Are Identical to the TL16C450 Register Set
• In the FIFO Mode, Transmitter and Receiver Are Each Buffered With 16-Byte FIFOs to Reduce the Number of Interrupts to the CPU
• In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
• Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (2¹⁶ -1) and Generates an Internal 16× Clock
• Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
• Independent Receiver Clock Input
• Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
• Fully Programmable Serial Interface Characteristics:
  • 5-, 6-, 7-, or 8-Bit Characters
  • Even-, Odd-, or No-Parity Bit Generation and Detection
  • 1-, 1 1/2-, or 2-Stop Bit Generation
  • Baud Generation (DC to 562 Kbit/s)
• False-Start Bit Detection
• Complete Status Reporting Capabilities
• 3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection
• Internal Diagnostic Capabilities:
  • Loopback Controls for Communications Link Fault Isolation
  • Break, Parity, Overrun, Framing Error Simulation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS\, RTS\, DSR\, DTR\, RI\, and DCD\)
• Faster Plug-In Replacement for National Semiconductor NS16550A

  ^[dagger]The TL16C550B and the TL16C550BI can also be reset to the TL16C450 mode under software control.

description

The TL16C550B and the TL16C550BI are functional upgrades of the TL16C450 asynchronous communications element (ACE). Functionally identical to the TL16C450 on power up (character mode^[dagger]), the TL16C550B and TL16C550BI can be placed in an alternate mode (FIFO) to relieve the CPU of excessive software overhead.

In this alternate FIFO mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (RXRDY\ and TXRDY\) have been changed to allow signalling of DMA transfers.

The TL16C550B and the TL16C550BI perform serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the ACE at any point in the ACE operation. Reported status information includes: the type of transfer operation in progress, the status of the operation, and any error conditions encountered.

The TL16C550B and the TL16C550BI ACE include programmable, on-board, baud rate generators. These generators are capable of dividing a reference clock input by divisors from 1 to (2¹⁶ -1) and producing a 16× clock for driving the internal transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that may be software tailored to user requirements to minimize the computing required to handle the communications link.

The TL16C550B is available in a 40-pin DIP (N) package, 44-pin PLCC (FN) package, and 48-pin TQFP (PT) package. The TL16C550BI is available in a 44-pin PLCC (FN) package.

View more information about generic part numbers:TL16C550B

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