SLLS026C - JANUARY 1987 - REVISED JULY 1990
The SN75061 is a single-channel driver/receiver pair designed for use in IEEE 802.3, 1BASE5 applications as well as other general data communications circuits. The SN75061 offers both a driver and a receiver that are easily configured for use with a variety of controllers and data encoder/decoders.
The receiver features a full analog squelch circuit with an adjustable threshold and a programmable squelch delay. Internal nodes of the squelch circuitry are brought out to external connections to allow for the insertion of noise-filtering circuitry of the designer's choice.
As with the receiver, the driver offers a variety of implementation options. Driver enabling may be directly controlled by an external logic input or by use of an on-chip one-shot that is retriggered as long as data is being sent to the driver. The driver then automatically goes to the high-impedance state when end-of-packet common phrase occurs. The driver features internal slew-rate control for optimal matching of rise and fall times allowing for reduction of driver-induced jitter.
The SN75061 receiver implements full analog squelch functions by integrating both a separate, parallel squelch receiver with an externally programmable threshold, and a programmable one-shot. The output of the squelch receiver and the input to the high-level, dc-triggered one-shot are brought out to external connections. These pins can be shorted for direct implementation or used for the insertion of noise-filtering circuitry of the implementer's design. The receiver one-shot can be effectively bypassed by applying a high logic level to SQDLI. The squelch threshold may be set externally by applying an external voltage set to a level that is -2 times the desired threshold voltage. When SQTHAJ is left open, the squelch receiver defaults to its internal preset value of -600 mV. The receiver also outputs a high logic squelch signal when there is not any active data present at the receiver inputs. When data is not present on the transmission line, the receiver output assumes a high level. The unsquelch duration is set externally with an R-C combination at SQDLAJ.
The driver offers a variety of implementation options. Driver enabling may be controlled directly by an active-low, external logic input on DATEN\ or by use of another on-chip one-shot that retriggers with positive-going transitions on the driver input line. When positive transition does not occur within the pulse duration set by an external R-C combination, the one-shot times out and the driver is automatically put into a high-impedance state. When operating in the delay-enable mode, the 2-bit-time, high-level, start-of-idle pulse prescribed by IEEE 802.3 1BASE5 causes the one-shot to time out and automatically place the driver outputs in the high-impedance state. This delay time is also adjustable for use in other applications. The driver implements an output slew-rate control that is internally set for nominally 40 mV/ns. (This is roughly a 100-ns peak-to-peak differential transition time.) The driver outputs are capable of driving a 50- differential load with a minimum output level of 2 V. Short-circuit output current is greater than 100 mA.
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