SLFS022 - SEPTEMBER 1973 - REVISED FEBRUARY 1992
These devices are precision monolithic timing circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle may be independently controlled with two external resistors and a single external capacitor.
The threshold and trigger levels are normally two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. RESET can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset and the output goes low. Whenever the output is low, a low-impedance path is provided between DISCH and ground.
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
The NE555 is characterized for operation from 0°C to 70°C. The SA555 is characterized for operation from -40°C to 85°C. The SE555 and SE555C are characterized for operation over the full military range of -55°C to 125°C.
View more information about generic part numbers:NE555, SA555, SE555
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