TMP320C50KGD, TMP320BC51KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE

SGZS008A - JULY 1996 - REVISED JUNE 1997

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features

• Fast Instruction Cycle Times of 35 ns and 50 ns
• Source-Code Compatible With all 'C1x and 'C2x Devices
• RAM-Based Operation
  • 9K-Words × 16-Bit Dual-Access On-Chip Program/Data RAM ('C50KGD Only)
  • 1K-Words × 16-Bit Single-Access On-Chip Program/Data RAM ('BC51 Only)
  • 1056-Word × 16-Bit Dual-Access On-Chip Data RAM
• 2K-Word × 16-Bit On-Chip Boot ROM ('C50KGD Only)
• 224K-Word × 16-Bit Maximum Addressable External Memory Space (64K-Word Program, 64K-Word Data, 64K-Word I/O, and 32K-Word Global)
• 8K-Word × 16-Bit On-Chip ROM With Boot Code ('BC51KGD Only)
• 32-Bit Arithmetic Logic Unit (ALU)
  • 32-Bit Accumulator (ACC)
  • 32-Bit Accumulator Buffer (ACCB)
• 16-Bit Parallel Logic Unit (PLU)
• 16 × 16-Bit Multiplier, 32-Bit Product
• Eleven Context Switch Registers
• Two Buffers for Circular Addressing
• Full-Duplex Synchronous Serial Port
• Time-Division Multiplexed Serial Port (TDM)
• Timer With Control and Counter Registers
• 16 Software Programmable Wait-State Generators
• Divide-By-1 Clock Option
• IEEE Standard 1149.1 Test Access Port
• Operations are Fully Static
• Fabricated Using the Texas Instruments Enhanced Performance Implanted CMOS (EPIC^TM) 0.72-um Technology

  IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture EPIC is a trademark of Texas Instruments Incorporated.

description

The TMP320C50KGD digital signal processor (DSP) is a high performance, 16-bit, fixed-point processor manufactured in 0.72-um double-level metal CMOS technology. The TMP320BC51KGD has the same functionality as the 'C50KGD except for a different memory configuration.

Texas Instruments Military Products currently employs three primary processes for the development of a known good die (KGD), one of which is applied to the TMP320C50 and TMP320BC51 devices. This process, known as hot-chuck-probe, uses a standard probed product that is tested again, this time at full data sheet specifications, in wafer form at speed and elevated temperature (85°C). Each individual die then is sawed, inspected, and packed for shipment. This flow produces a bare die that has been temperature-tested at speed and is known to be good, without having to use a temporary package.

A number of enhancements to the basic 'C2x architecture give the 'C5x a minimum 2x performance over the previous generation. A four-deep instruction pipeline, incorporating delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the 'C5x to perform instructions in fewer cycles. The addition of a PLU gives the 'C5x a method of manipulating bits in data memory without using the accumulator and ALU. The 'C5x has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory.

With the addition of the IDLE2 instruction, the 'C5x achieves low-power consumption. IDLE2 removes the functional clock from the internal hardware of the 'C5x that puts it into a total-sleep mode using only 5 uA. A low-logic level on an external interrupt with chip duration of at least five clock cycles ends the IDLE2 mode.

For electrical and timing specifications, see the TMS320C5x, TMS320LC5x Digital Signal Processors data sheet, literature number SPRS030.

View more information about generic part numbers:TMP320BC51KGD, TMP320C50KGD

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