SMJ320C50A DIGITAL SIGNAL PROCESSOR

SGUS018 - JANUARY 1994

features

Military Operating Temperature Range: - 55°C to 125°C
Processed to MIL-STD-883, Class B
Fast Instruction Cycle Times of 40 ns and 50 ns
Source-Code Compatible With All 'C1x and 'C2x Devices
RAM-Based Operation
- 9K × 16-Bit Single-Cycle On-Chip Program/Data RAM
- 1056 × 16-Bit Dual-Access On-Chip Data RAM
2K × 16-Bit On-Chip Boot ROM
224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global)
32-Bit Arithmetic Logic Unit (ALU)
- 32-bit Accumulator (ACC)
- 32-Bit Accumulator Buffer (ACCB)
16-Bit Parallel Logic Unit (PLU)
16 × 16-Bit Multiplier, 32-Bit Product
11 Context-Switch Registers
2 Buffers for Circular Addressing
Full-Duplex Synchronous Serial Port
Time-Division Multiplexed Serial Port (TDM)
Timer With Control and Counter Registers
16 Software Programmable Wait-State Generators
Divide-by-One Clock Option
JTAG Boundary Scan Logic (IEEE 1149.1)
Operations Are Fully Static
Texas Instruments EPIC^TM 0.8-um CMOS Technology
Packaging
- 141-Pin Ceramic Grid Array (GFA Suffix)
- 132-Lead Ceramic Quad Flat Package (HFG Suffix)
  EPIC is a trademark of Texas Instruments Incorporated.

description

The SMJ320C50A digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor manufactured in 0.8-um double-level metal CMOS technology. The SMJ320C50A is the first DSP from TI designed as a fully static device. Full-static CMOS design contributes to low power consumption while maintaining high performance, making it ideal for applications such as battery-operated communications systems, satellite systems, and advanced control algorithms.

A number of enhancements to the basic SMJ320C2x architecture give the 'C50A a minimum 2× performance over the previous generation. A four-deep instruction pipeline, incorporating delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the 'C50A to perform instructions in fewer cycles. The addition of a parallel logic unit (PLU) gives the 'C50A a method of manipulating bits in data memory without using the accumulator and ALU. The 'C50A has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory.

The 'C50A achieves its low power consumption through the IDLE2 instruction. IDLE2 removes the functional clock from the internal hardware of the 'C50A, which puts it into a total-sleep mode that uses only 5 uA. A low logic level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.

The 'C50A is available with two clock speeds. The clock frequencies are 40 MHz, giving a 50-ns cycle time, and 50 MHz, giving a 40-ns cycle time.

Title: DIGITAL SIGNAL PROCESSOR
Product Family: TMS320C5X FIXED POINT DSP
Device Functionality: 16 BIT FIXED POINT,5V
Orderable Devices: 5962-9455801QXA, 5962-9455801QYA, 5962-9455802QXA, 5962-9455802QYA, SM320C50AGFAM40, SM320C50AGFAM50, SM320C50AHFGM40, SM320C50AHFGM50, SMJ320C50AGFAM40, SMJ320C50AGFAM50, SMJ320C50AHFGM40, SMJ320C50AHFGM50

View the complete PDF datasheet: sgus018.pdf (485 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SMJ320C50A

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