SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS

SGUS017B - OCTOBER 1993 - REVISED MARCH 1998

features

SMJ: QML Processing to MIL-PRF-38535
SM: Standard Processing
TMP: Commercial Level Processing TAB
Operating Temperature Ranges:
- Military (M) -55°C to 125°C
- Special (S) -55°C to 100°C
- Commercial (C) -25°C to 85°C
- Commercial (L) 0°C to 70°C
Highest Performance Floating-Point Digital Signal Processor (DSP)
- 'C40-60: 33-ns Instruction Cycle Time: 60 MFLOPS, 30 MIPS, 330 MOPS, 384 MBps
- 'C40-50: 40-ns Instruction Cycle Time: 50 MFLOPS, 25 MIPS, 275 MOPS, 320 MBps
- 'C40-40: 50-ns Instruction Cycle Time: 40 MFLOPS, 20 MIPS, 220 MOPS, 256 MBps
Six Communications Ports
6-Channel Direct Memory Access (DMA) Coprocessor
Single-Cycle Conversion to and From IEEE-745 Floating-Point Format
Single Cycle 1/x, 1/
Source-Code Compatible With SMJ320C30
Validated Ada Compiler
Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers
12 40-Bit Registers, 8 Auxiliary Registers, 14 Control Registers, and 2 Timers
IEEE Standard 1149.1^† Test-Access Port (JTAG)
Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers:
- High Port-Data Rate of 100 MBytes/s (Each Bus)
- 16G-Byte Continuous Program/Data/Peripheral Address Space
- Memory-Access Request for Fast, Intelligent Bus Arbitration
- Separate Address-, Data-, and Control-Enable Pins
- Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
Packaging:
- 325-Pin Ceramic Grid Array (GF Suffix)
- 352-Lead Ceramic Quad Flatpack (HFH Suffix)
- 324-Pad JEDEC-Standard TAB Frame
Fabricated Using 0.72-um Enhanced Performance Implanted CMOS (EPIC^TM) Technology by Texas Instruments (TI^TM)
Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance
On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
- 512-Byte Instruction Cache
- 8K Bytes of Single-Cycle Dual-Access Program or Data RAM
- ROM-Based Bootloader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories Over Any One of the Communications Ports
  ^†IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture. EPIC and TI are trademarks of Texas Instruments Incorporated.

description

^† See the pin assignments tables and the signal description table for location and description of all pins.

The '320C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-um, double-level metal CMOS technology. The '320C40 is a part of the fourth-generation DSPs from Texas Instruments and is designed primarily for parallel processing.

Title: DIGITAL SIGNAL PROCESSORS
Product Family: TMS320C4X FLOATING POINT DSP
Device Functionality: 32 BIT FLOATING POINT,5V,PARALEL PROCESSING
Orderable Devices: 5962-9466902QYC, 5962-9466903QYC, SM320C40GFM40, SMJ320C40GFM33, SMJ320C40GFM40, SMJ320C40GFM50, SMJ320C40GFS60, SMJ320C40HFHM33, SMJ320C40HFHM40, SMJ320C40HFHM50, SMJ320C40HFHS60, SMJ320C40TABM40, SMJ320C40TABM50, SMJ320C40TABS60, SMJ320C40TBBM40, SMJ320C40TBBM50, SMJ320C40TBBS60

View the complete PDF datasheet: sgus017b.pdf (1157 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SMJ320C40

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.