SGMS734A - MAY 1996 - REVISED JUNE 1997
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The SMJ5C1008 is a high-performance 1048576-bit CMOS static random-access memory (SRAM) organized as 128K words × 8 bits. The device features maximum address or chip-enable access times of 20 ns or 25 ns.
The SMJ5C1008 offers dual chip enables (CE1\, CE2) and an output enable (OE\) for greater system flexibility. The chip enables place the device in an active or standby-power mode, while
OE\ allows the outputs to be placed in the high-impedance state, eliminating bus contention problems. In the standby-power mode, the device is disabled, resulting in reduced power consumption. This allows designers to meet extremely low standby-power requirements.
To write to the device, the WE\ and CE1\ inputs are held at logic low while CE2 is at logic high. To read from the device, WE\ and CE2 are held at logic high and CE1\ and OE\ are held at logic low.
All devices operate from a single 5-V (±10%) supply. They are MIL-PRF-38535, Device Class Q qualified and are operational from -55°C to 125°C.
View more information about generic part numbers:SMJ5C1008
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