SMJ320MCM42C, SMJ320MCM42D DUAL SMJ320C40 MULTICHIP MODULE

SGKS001 - JULY 1997

On products compliant to MIL-STD-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Performance:
  • 80 Million Floating-Point Operations Per Second (MFLOPS) With 496-MBps-Burst I/O Rate for 40-MHz Modules
  • Zero-Wait-State Local Memory for Each Processor
• Organization:
  • 128K-Word × 32-Bit Static Random-Access Memory (SRAM) (SMJ320MCM42D)
  • 256K-Word × 32-Bit SRAM (SMJ320MCM42C)
• Compliant With MIL-PRF-38535 QML
• Dual 'C40 Performance With Local Memory Requiring Only 8.7 Square Inches of Board Space
• Enhanced Performance Offered By Multichip-Module Solution
  • SMJ320MCM42C
    • - 67% Reduction in Number of Interconnects
    • - 54% Reduction (Minimum) in Board Area
    • - Estimated 38% Reduction in Power Dissipation Due to Reduced Parasitic Capacitance and Interconnect Lengths
  • SMJ320MCM42D
    • - 56% Reduction in Number of Interconnects
    • - 30% Reduction (Minimum) in Board Area
    • - Estimated 20% Reduction in Power Dissipation Due to Reduced Parasitic Capacitance and Interconnect Lengths
• Four Memory Ports for High Data Bandwidth
  • Two Full 2G-Word External Buses
• Two Internal Buses Mapped to Memory
  • 128K-Word × 32-Bit SRAM for Each 'C40 Local Bus (SMJ320MCM42D)
  • 256K-Word × 32-Bit SRAM for Each 'C40 Local Bus (SMJ320MCM42C)
• Ten External Communication Ports for Direct Processor-to-Processor Communication
• IEEE-1149.1 (JTAG) Boundary-Scan Compatible
• 408-Lead Ceramic Quad Flatpack Package (HFN Suffix)
• Operating Free-Air Temperature Ranges:
• -55°C to 125°C...(Military)
• 0°C to 70°C...(Commercial)
• Communication-Port Connection Provided Between 'C40s for Interprocessor Communication

  IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary-Scan Architecture

description

The '42 dual 'C40 multichip module (MCM) contains two SMJ320C40 digital signal processors (DSPs) with 128K words × 32 bits ('42D) or 256K words × 32 bits ('42C) of zero-wait-state SRAMs mapped to each local bus. Global address and data buses with two sets of control signals are routed externally for each processor, allowing external memory to be accessed. The external global bus provides a continuous address reach of 2G words.

The dual 'C40 configuration allows standard microprocessor initialization using the bootstrap loader. Both reset-vector-control terminals are brought out to external terminals for each processor. A single CLKIN line and a RESET line feed both processors in parallel, minimizing clock skew and allowing easy synchronization for interlocked operations.

Communication port 0 of CPU #1 connects to communication port 3 of CPU #2 for direct processor-to-processor communication.

The IEEE-1149.1 (JTAG) test ports of the 'C40s are connected serially to allow scan operations and emulation of the module as a whole. Testability of the '42 adds value and reduces development and support costs. Texas Instruments (TI^TM) offers a wide variety of ANSI/IEEE-1149.1 products and support.

The '42 dual 'C40 MCM is packaged in a 408-pin ceramic quad flat pack. The '42 dual 'C40 MCM is available in both a commercial temperature range (0°C to 70°C) and a military temperature range (-55°C to 125°C) option.

View more information about generic part numbers:SM320MCM42C, SM320MCM42D, SMJ320MCM42C, SMJ320MCM42D

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