SGBS311 - FEBRUARY 1997
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The SN54CDC586 is a high-performance, low-skew, low-jitter clockdriver. It uses a phase-lock loop (PLL) to precisely align, in bothfrequency and phase, the clock output signals to the clock input(CLKIN) signal. It is specifically designed for use with popularmicroprocessors operating at speeds from 50 MHz to 100 MHz, or downto 25 MHz on outputs configured as half-frequency outputs. TheSN54CDC586 operates at 3.3-V VCC and is designed to drivea properly terminated 50- transmission line.
The feedback input (FBIN) is used to synchronize the output clocksin frequency and phase to CLKIN. One of the 12 output clocks must befed back to FBIN for the PLL to maintain synchronization between theCLKIN input and the outputs. The output used as the feedback pin issynchronized to the same frequency as the CLKIN input.
The Y outputs can be configured to switch in phase and at the samefrequency as CLKIN. Select inputs (SEL1, SEL0) configure up to nine Youtputs, in banks of three, to operate at one-half or double theCLKIN frequency, depending on which pin is fed back to FBIN (seeTables 1 and 2). All output-signal duty cycles are adjusted to 50%,independent of the duty cycle at CLKIN.
Output-enable (
) is providedfor output control. When ishigh, the outputs are in the high-impedance state. When 
isnegative-edge triggered and can be used to reset the outputsoperating at half frequency. TEST is used for factory testing of thedevice and can be used to bypass the PLL. TEST should be strapped toGND for normal operation.
Unlike many products containing PLLs, the SN54CDC586 does notrequire external RC networks. The loop filter for the PLL is includedon chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the SN54CDC586 requires astabilization time to achieve phase lock of the feedback signal tothe reference signal. This stabilization time is required, followingpower up and application of a fixed-frequency, fixed-phase signal atCLKIN, as well as following any changes to the PLL reference orfeedback signals. Such changes occur upon change of the selectinputs, enabling of the PLL via TEST, and upon enable of all outputsvia .
The SN54CDC586 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C.
The voltage-controlled oscillator (VCO) used in the SN54CDC586 PLLhas a frequency range of 100 MHz to 200 MHz, twice the operatingfrequency range of the SN54CDC586 outputs. The output of the VCO isdivided by two and by four to provide reference frequencies with a50% duty cycle of one-half and one-fourth the VCO frequency. SEL0 andSEL1 select which of the two signals are buffered to each bank ofdevice outputs.
One device output must be externally wired to FBIN to complete thePLL. The VCO operates such that the frequency and phase of thisoutput match that of CLKIN. In the case in which a VCO/2 output iswired to FBIN, the VCO must operate at twice the CLKIN frequency,resulting in device outputs that operate at either the same orone-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, thedevice outputs operate at twice or the same frequency as the CLKINfrequency.
Output configuration A is valid when any output configured as a 1xfrequency output in Table 1 is fed back to FBIN. The input frequencyrange for CLKIN is 50 MHz to 100 MHz when using output configurationA. Outputs configured as 1/2x outputs operate at one-half the CLKINfrequency, while outputs configured as 1x outputs operate at the samefrequency as CLKIN.
Output configuration B is valid when any output configured as a 1xfrequency output in Table 2 is fed back to FBIN. The input frequencyrange for CLKIN is 25 MHz to 50 MHz when using output configurationB. Outputs configured as 1x outputs operate at the CLKIN frequency,while outputs configured as 2x outputs operate at double thefrequency of CLKIN.
View more information about generic part numbers:SN54CDC586
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