SGBS303D - AUGUST 1994 - REVISED APRIL 1998
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A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN54ABT7820 is arranged as two 512 × 18-bit FIFOs for high speed and fast access times. It processes data at rates up to 67 MHz, with access times of 12 ns in a bit-parallel format.
The SN54ABT7820 consists of bus transceiver circuits, two 512 × 18 FIFOs, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs GAB and GBA control the transceiver functions. The SAB and SBA control inputs select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight fundamental bus-management functions that can be performed with the SN54ABT7820.
The SN54ABT7820 is characterized for operation over the full military temperature range of -55°C to 125°C.
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