SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE

SDZS13A - APRIL 1990 - REVISED OCTOBER 1990

features

• 100K Compatible
• TTL Clock and ECL Control Inputs
• Noninverting Outputs
• Flow-Through Architecture Optimizes PCB Layout
• Center Pin V_CC, V_EE, and GND Configurations Minimize High-Speed Switching Noise
• Package Options Include "Small Outline" Packages and Standard Plastic DIPs
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015

description

This octal TTL-to-ECL translator is designed to provide efficienttranslation between a TTL signal environment and a 100K ECL signalenvironment. This device is designed specifically to improve theperformance and density of TTL-to-ECL CPU/bus-oriented functions suchas memory-address drivers,clock drivers, and bus-oriented receiversand transmitters.

The eight flip-flops of the '5578 are edge-triggered D-typeflip-flops. On the positive transition of the clock, the Q outputsare set to the logic levels that were set up at the D inputs.

The output-control input doesnot affect the internal operations of the flip-flops. Old data can beretained or new data can be entered while the outputs are off.

The SN100KT5578 is characterized for operation from 0°C to85°C.

View more information about generic part numbers:SN100KT5578

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