SDZS015 - MAY 1990 - REVISED OCTOBER 1990
This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The eight latches of the SN10KHT5573 are transparent D-type latches. While latch enable (LE\) is low, the Q outputs follow the data (D) inputs. When LE\ is high, the Q outputs are latched at the levels that were set up at the D inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components. Output-enable OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
The SN10KHT5573 is characterized for operation from 0° to 75°C.
View more information about generic part numbers:SN10KHT5573
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