SN100 T5574 OCTAL ECL-TO-TTLTRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS

features

• 100K Compatible
• ECL Clock and TTL Control Inputs
• Flow-Through Architecture Optimizes PCB Layout
• Center Pin V_CC, V_EE, and GND Configurations Minimize High-Speed Switching Noise
• Package Options Include "Small Outline" Packages and Standard Plastic DIPs

description

This octal ECL-to-TTL translator is designed to provide efficienttranslation between a 100K ECL signal environment and a TTL signalenvironment.

This device is designed specifically to improve the performanceand density of ECL-to-TTL CPU/bus-oriented functions such asmemory-address drivers, clock drivers, and bus-oriented receivers andtransmitters.

The eight flip-flops of the SN100KT5574 are edge-triggered D-typeflip-flops. On the positive transition of the clock, the Q outputsare set to the logic levels that were set up at the D inputs.

A buffered output-enable input () can be used to place the eightoutputs in either a normal logic state (high or low logic levels) ora high-impedance state. In the high-impedance state, the outputsneither load nor drive the bus lines significantly. Thehigh-impedance third state and increased drive provide the capabilityto drive bus lines without need for interface or pullup components.

The output-enable input does not affect the internal operations of theflip-flops. Old data can be retained or new data can be entered whilethe outputs are off.

The SN100KT5574 is characterized for operation from 0°C to85°C.

View more information about generic part numbers:SN100KT5574

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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