SDNS042A - AUGUST 1997 - REVISED JANUARY 1998
The synchronous optical network (SONET)/synchronous digital hierarchy (SDH) asynchronous transport mode (ATM) line-interface receiver/transmitter provides a single-chip implementation for transporting ATM cells over the SONET/SDH network at the STS-3c/STM-1 rate of 155.52 Mbits/s. This device provides all the functionality required to insert and extract 53-byte ATM cells into/from an STS-3c/STM-1 synchronous payload envelope (SPE), including clock recovery and clock generation using analog phase-locked loops (APLL).
On the receive side, the TNETA1500A accepts 155.52-Mbit/s serial data, recovers the embedded clock signal, performs SONET/SDH frame alignment and serial-to-parallel conversion, identifies the SONET/SDH payload, and establishes the ATM-cell boundaries. The ATM cells are extracted from the payload, descrambled, and passed to the receive output FIFO for output to the next device (i.e., a reassembly device). On the transmit side, complete 53-byte ATM cells are placed in the transmit input FIFO, scrambled, and inserted into an STS-3c/STM-1 SPE. The SONET/SDH frame is scrambled and converted to a serial-data stream for output. An APLL is used to generate the 155.52-MHz output clock from a low-speed 19.44-MHz oscillator, eliminating the need for a high-speed 155.52-MHz oscillator.
View more information about generic part numbers:TNETA1500A
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