SDNS028D - OCTOBER 1994 - REVISED JANUARY 1998
The TNETA1561 (PCI SAR) is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with a peripheral component interconnect (PCI)-bus interface. This device incorporates ATM adaptation-layer (AAL) processing, ATM SAR processing for full-duplex operation up to STS-3c rate of 155.52 Mbit/s, and the controls for the register interface on the physical (PHY) layer. The TNETA1561 provides a packet interface that is managed by descriptor rings, making the 53-byte ATM-framing format transparent to the user. The device passes the payload of 48 bytes, constituting the payload of each cell, across the PCI-host interface. All packets are segmented and reassembled in host memory and accessed by the chip via the descriptor-ring mechanism. The device reduces the memory requirements for network-interface cards (NICs). The TNETA1561 requires no local processor on the card, which enables very compact solutions.
The applications for the TNETA1561 include NICs for client workstations and servers, embedded applications like LAN emulation, and multiprotocol systems like video servers. The TNETA1561 provides complete AAL5 encapsulation and termination in hardware. In addition, limited support is provided for AAL 3/4 and a null AAL is provided to facilitate real-time data transfer. The TNETA1561 recognizes ATM-layer operation and maintenance (OAM) cells.
In the transmit direction, the TNETA1561 generates data via a special bit-rate control table that provides explicit cell-level interleaving between groups of virtual circuits (VCs). This mechanism brings a higher degree of flexibility when specifying peak rates for each group (up to 155.52 Mbit/s at a resolution greater than 32 kbit/s). The VCs within a group are serviced via a first-in, first-out (FIFO) discipline on a per-packet basis.
In the receive direction, the TNETA1561 allows multiple virtual paths (VPs) with the condition that each VC is unique. The device is primarily intended for AAL5 encapsulation and termination that is supported in hardware.
The TNETA1561 has four interfaces that include the following: the PCI-bus interface with a 32-bit-wide data bus, the cell interface based on the universal test and operations interface for ATM (UTOPIA specification), a control-memory interface to access the local SRAM, and the local-bus interface to access the PHY-layer registers. The UTOPIA interface to the PHY layer consists of an 8-bit-wide datapath and associated control signals in both the transmit and receive directions. The 53-byte ATM cells pass between the ATM and PHY layers through the UTOPIA interface.
The native clock for the TNETA1561 is the PCI clock, which operates up to 33 MHz. The native-word size for the device is 32 bits, corresponding to the data width for the PCI bus. The TNETA1561 host interface implements the bus protocol defined in the PCI local-bus specification (revision 2.0). The control-memory interface is 32 bits wide. This interface allows the device to access the local memory to obtain the control information on the packets being segmented and reassembled and to obtain their locations in host memory. Each packet queued for transmission can be distributed across multiple buffers in host memory, with each starting at any byte boundary. This is supported in hardware by the device. Every received package is placed in a single buffer in the host memory and is aligned to a 16-byte boundary. The TNETA1561 operation is explained in detail in the Principles of Operation section.
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