TNETA1560 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH SBUS HOST INTERFACE

SDNS010C - JANUARY 1994 - REVISED OCTOBER 1995

features

• SBus Device That Provides Asynchronous Transfer-Mode Interface
• Single-Chip Segmentation and Reassembly (SAR) for Full-Duplex ATM Adaptation- Layer (AAL) Processing
• On-Chip SBus Host Interface Allows Use of Host Memory for Packet SAR
• 53-Byte ATM Cells Are Transparent to the User
• Provides Complete Encapsulation and Termination of AAL5 and Limited AAL3/4
• Features a Null AAL That Provides Functions for Constant-Bit-Rate Services
• Supports 1023 Unique Virtual Circuits (VCs) on Receive Side
• Explicit Cell-Level Interleaving Between Groups of VCs
• Packet Interface Is Managed by Efficient Descriptor Rings
• Physical (PHY)-Layer Interface Is Full Duplex
• Supports PHY-Layer Data Rates in the Range of 25.6 Mbit/s to 155.52 Mbit/s
• Interfaces Directly to the TNETA1500 SONET ATM BiCMOS Receiver/Transmitter (SABRE)
• Recognizes ATM-Layer Operation and Maintenance (OAM) Cells
• No External Logic Required for Host Bus to Ensure Simple Design

description

The TNETA1560 is an asynchronous transfer mode (ATM) segmentationand reassembly (SAR) device with an SBus interface. This deviceincorporates ATM adaptation-layer (AAL) processing, ATM SARprocessing for full-duplex operation up to the STS-3c rate of 155.52Mbit/s, and the controls for the register interface on the physical(PHY) layer. The device provides a packet interface that is managedby descriptor rings, making the 53-byte ATM-framing formattransparent to the user. The device passes the payload of 48 bytes,constituting the payload of each cell, across the SBus-hostinterface. All packets are segmented and reassembled in host memoryand accessed by the chip via the descriptor-ring mechanism. Thisoperation reduces the memory requirements for network-interface cards(NICs). The TNETA1560 requires no local processor on the card, whichenables very compact solutions.

The applications for the TNETA1560 include NICs for clientworkstations and servers, embedded applications like LAN emulation,and multiprotocol systems like video servers. The TNETA1560 providescomplete AAL5 encapsulation and termination in hardware. In addition,limited support is provided for AAL3/4 and a null AAL is provided tofacilitate real-time data transfer. The TNETA1560 recognizesATM-layer operation and maintenance (OAM) cells.

In the transmit direction, the TNETA1560 generates data via aspecial bit-rate control table that provides explicit cell-levelinterleaving between groups of virtual circuits (VCs). This mechanismbrings a higher degree of flexibility when specifying peak rates foreach group (up to 155.52 Mbit/s at a resolution greater than 32kbit/s). The VCs within a group are serviced via a first-in,first-out (FIFO) discipline on a per-packet basis.

In the receive direction, the TNETA1560 allows multiple virtualpaths (VPs) with the condition that each VC is unique. The device isprimarily intended for AAL5 encapsulation and termination that issupported in hardware.

The TNETA1560 has four interfaces that include: the SBus interfacewith a 32-bit-wide data bus, the cell interface, a control-memoryinterface to access the local SRAM, and the local-bus interface toaccess the PHY-layer register and an EPROM. The cell interface to thePHY layer consists of an 8-bit-wide data path and associated controlsignals in both the transmit and receive directions. The 53-byte ATMcells pass between the ATM and PHY layers.

View more information about generic part numbers:TNETA1560

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