SDNS001B - SEPTEMBER 1992 - REVISED DECEMBER 1994
The TNETA1555 device recovers an embedded clock signal from a155.52-Mbit/s STS-3/STM-1 nonreturn-to-zero (NRZ) data stream using afrequency/phase-locked loop. The device accepts PECL (ECL signalsreferenced to 5 V instead of GND) input-voltage levels. The recoveredclock and data outputs are PECL compatible. The serial data input andrecovered clock and data outputs are differential to provide maximumnoise immunity.
The input disable (INDIS) disconnects the incoming serial datastream from the clock-recovery circuitry. When the INDIS input ishigh, the data output is forced low and the clock-recovery circuitrymaintains the output frequency present at the time the input wasdisabled for a specific amount of time. This time is dependent uponthe value of the capacitor in the loop filter.
A PECL-to-ECL converter is included in the device for thoseapplications where an interface between the two different voltagelevels is required. An example of such an application is an opticaltransmitter that requires ECL input voltage levels and aparallel-to-serial converter with pseudo-ECL-level outputs.
The TNETA1555 requires only a positive 5-V supply (5 V ± 5 %)for operation. The device is characterized for operation over atemperature range of -40°C to 85°C.
View more information about generic part numbers:TNETA1555
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