SDLS193 - MARCH 1974 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
The SN54LS670 and SN74LS670 MSI 16-bit TTL register files incorporate theequivalent of 98 gates. The register file is organized as 4 words of 4 bitseach and separate on-chip decoding is provided for addressing the four wordlocations to either write-in or retrieve data. This permits simultaneous writinginto one location and reading from another word location.
Four data inputs are available which are used to supply the 4-bit wordto be stored. Location of the word is determined by the write-address inputsA and B in conjunction with a write-enable signal. Data applied at the inputsshould be in its true form. That is, if a high-level signal is desired fromthe output, a high-level is applied at the data input for that particularbit location. The latch inputs are arranged so that new data will be acceptedonly if both internal address gate inputs are high. When this condition exists,data at the D input is transferred to the latch output. When the write-enableinput, G\W, is high, the data inputs are inhibited andtheir levels can cause no change in the information stored in the internallatches. When the read-enable input, G\R, is high, thedata outputs are inhibited and go into the high-impedance state.
The individual address lines permit direct acquisition of data stored inany four of the latches. Four individual decoding gates are used to completethe address for reading a word. When the read address is made in conjunctionwith the read-enable signal, the word appears at the four outputs.
This arrangement — data-entry addressing separate from data-readaddressing and individual sense line — eliminates recovery times, permitssimultaneous reading and writing, and is limited in speed only by the writetime (27 nanoseconds typical) and the read time (24 nanoseconds typical).The register file has a nondestructive readout in that data is not lost whenaddressed.
All inputs except read enable and write enable are buffered to lower thedrive requirements to one Series 54LS/74LS standard load, and input-clampingdiodes minimize switching transients to simplify system design. High-speed,double-ended AND-OR-INVERT gates are employed for the read-address functionand have high-sink-current, three-state outputs. Up to 128 of these outputsmay be bus connected for increasing the capacity up to 512 words. Any numberof these registers may be paralleled to provide n-bit word length.
The SN54LS670 is characterized for operation over the full military temperaturerange of -55°C to 125°C; the SN74LS670 is characterized for operationfrom 0°C to 70°C.
View more information about generic part numbers:SN54LS670, SN74LS670
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