SDLS192 - APRIL 1977 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters
These synchronous presettable counters feature an internal carry look-aheadfor cascading in high-speed counting applications. The 'LS668 are decade countersand the 'LS669 are 4-bit binary counters. Synchronous operation is providedby having all flip-flops clocked simultaneously so that the outputs changecoincident with each other when so instructed by the count-enable inputs andinternal gating. This mode of operation helps eliminate the output countingspikes that are normally associated with asynchronous (ripple-clock) counters.A buffered clock input triggers the four master-slave flip-flops on the rising(positive-going) edge of the clock waveform.
These counters are fully programmable; that is, the outputs may each bepreset to either level. The load input circuitry allows loading with the carry-enableoutput of cascaded counters. As loading is synchronous, setting up a low levelat the load input disables the counter and causes the outputs to agree withthe data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bitsynchronous applications without additional gating. Instrumental in accomplishingthis function are two count-enable inputs and a carry output. Both count enableinputs (P\ and T\) must be low to count. The directionof the count is determined by the level of the up/down input. When the inputis high, the counter counts up; when low, it counts down. Input T\is fed forward to enable the carry output. The carry output thus enabled willproduce a low-level output pulse when the count is maximum counting up orzero counting down. This low-level overflow carry pulse can be used to enablesuccessive cascaded stages. Transitions at the enable P\ or T\ inputs are allowed regardless of the level of the clock input. Allinputs are diode-clamped to minimize transmission-line effects, thereby simplifyingsystem design.
These counters feature a fully independent clock circuit. Changes at controlinputs (enable P\, enable T\, load, up/down) that willmodify the operating mode have no effect until clocking occurs. The functionof the counter (whether enabled, disabled, loading, or counting) will be dictatedsolely by the conditions meeting the stable setup and hold times.
The 'LS668 and 'LS669 are completely new designs. Compared to the original'LS168 and 'LS169, they feature 0-nanosecond minimum hold time, reduced inputcurrents IIH and IIL, and all buffered outputs.
View more information about generic part numbers:SN54LS669, SN74LS668, SN74LS669
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