SDLS172 - OCTOBER 1976 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all paramenters.
These 4-bit registers feature parallel inputs, parallel outputs, and clock(CLK), serial (SER), load shift (LD/SH\), output control (OC\) and direct overriding clear (CLR\) inputs.
Shifting is accomplished when the load/shift control is low. Parallel loadingis accomplished by applying the four bits of data and taking the load/shiftcontrol input high. The data is loaded into the associated flip-flops andappears at the outputs after the high-to-low transition of the clock input.During parallel loading, the entry of serial data is inhibited.
When the output control is low, the normal logic levels of the four outputsare available for driving the loads or bus lines. The outputs are disabledindependently from the level of the clock by a high logic level at the outputcontrol input. The outputs then present a high impedance and neither loadnor drive the bus line; however, sequential operation of the registers isnot affected. During the high-impedance mode, the output at QD'is still available for cascading.
View more information about generic part numbers:SN54LS395A, SN74LS395A
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