SDLS167 - OCTOBER 1976 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitryto implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378,and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively,but feature a common enable instead of a common clear.
Information at the D inputs meeting the setup time requirements is transferredto the Q outputs on the positive-going edge of the clock pulse if the enableinput G\ is low. Clock triggering occurs at a particular voltagelevel and is not directly related to the transition time of the positive-goingpulse. When the clock input is at either the high or low level, the D inputsignal has no effect at the output. The circuits are designed to prevent falseclocking by transitions at the G\ input.
These flip-flops are guaranteed to respond to clock frequencies rangingfrom 0 to 30 MHz while maximum clock frequency is typically 40 megahertz.Typical power dissipation is 10 milliwatts per flip-flop.
View more information about generic part numbers:SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379
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