SDLS165 - OCTOBER 1975 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
These 8-bit registers feature three-state outputs designed specificallyfor driving highly-capacitive or relatively low-impedance loads. The high-impedancethird state and increased high-logic-level drive provide these registers withthe capability of being connected directly to and driving the bus lines ina bus-organized system without need for interface or pull-up components. Theyare particularly attractive for implementing buffer registers, I/O ports,bidirectional bus drivers, and working registers.
The eight latches of the 'LS373 and 'S373 are transparent D-type latchesmeaning that while the enable (C) is high the Q outputs will follow the data(D) inputs. When the enable is taken low the output will be latched at thelevel of the data that was set up.
The eight flip-flops of the 'LS374 and 'S374 are edge-triggered D-typeflip-flops. On the positive transition of the clock, the Q outputs will beset to the logic states that were setup at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the 'S373and 'S374 devices, simplify system design as ac and dc noise rejection isimproved by typically 400 mV due to the input hysteresis. A buffered outputcontrol input can be used to place the eight outputs in either a normal logicstate (high or low logic levels) or a high-impedance state. In the high-impedancestate the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of the latchesor flip-flops. That is, the old data can be retained or new data can be enteredeven while the outputs are off.
View more information about generic part numbers:SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374
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