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Data Sheet Abstract

SN54LS297, SN74LS297 DIGITAL PHASE-LOCKED-LOOP FILTERS

SDLS155 - JANUARY 1981 - REVISED MARCH 1988


PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.

features

 

description

The SN54LS297 and SN74LS297 devices are designed to provide a simple, cost-effectivesolution to high-accuracy, digital, phase-locked-loop applications. Thesedevices contain all the necessary circuits, with the exception of the divide-by-Ncounter, to build first order phase-locked loops as described in Figure 1.

Both exclusive-OR (XORPD) and edge-controlled (ECPD) phase detectors areprovided for maximum flexibility.

Proper partitioning of the loop function, with many of the building blocksexternal to the package, makes it easy for the designer to incorporate ripplecancellation or to cascade to higher order phase-locked loops.

The length of the up/down K counter is digitally programmable accordingto the K counter function table. With A, B, C, and D all low, the K counteris disabled. With A high and B, C, and D low, the K counter is only threestages long, which widens the bandwidth or capture range and shortens thelock time of the loop. When A, B, C, and D are all programmed high, the Kcounter becomes seventeen stages long, which narrows the bandwidth or capturerange and lengthens the lock time. Real-time control of loop bandwidth bymanipulating the A through D inputs can maximize the overall performance ofthe digital phase-locked loop.FIGURE 1-SIMPLIFIED BLOCK DIAGRAM

The 'LS297 can perform the classic first-order phase-locked loop functionwithout using analog components. The accuracy of the digital phase-lockedloop (DPLL) is not affected by VCC and temperature variations,but depends solely on accuracies of the K clock, I/D clock, and loop propagationdelays. The I/D clock frequency and the divide-by-N modulos will determinethe center frequency of the DPLL. The center frequency is defined by the relationshipfc = I/D Clock /2N(Hz).

 


Title: DIGITAL PHASE-LOCKED-LOOP FILTERS
Product Family: OTHER DIGITAL LOGIC
Device Functionality: DIGITAL PLL FILTER
Orderable Devices: SN74LS297N

View the complete PDF datasheet: sdls155.pdf (324 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LS297

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